USING SAT-BASED CRAIG INTERPOLATION TO ENLARGE CLOCK GATING FUNCTIONS Ting-Hao Lin, Chung-Yang (Ric) Huang Graduate Institute of Electrical Engineering, National Taiwan University, Taiwan DAC’11

Outline  Introduction  Preliminaries  Algorithm  Implementation  Experimental results  Conclusion

Introduction  Portable and mobile devices: how to reduce the power consumption in order to prolong the battery life between recharges.  Roughly 70% of the dynamic power is consumed by the clock trees and their latch loads [1].  Not all of the clock switching and latch loads are necessary in circuit operations. -clock gating

 The clock gating mechanism saves the power by reducing the data loading of the gated registers.  However, it should not alter their functionalities.

 Synthesis the gating logic -provide the full controllability on the synthesis of the clock gating signal to find the optimal power consumption. -substantial timing or area overheads to the circuit  SAT-based method (refer as Hurst’s algorithm) -searches for internal nets as valid gating signals -minimal overhead in gating logic -Hurst’s algorithm has no flexibility in synthesizing gating logic

 This paper extends Hurst’s algorithm by constructing the interpolants of the SAT proofs as the clock gating signals.  Our proposed algorithm can lead to better power saving than Hurst’s algorithm with a slightly area overhead from the interpolant circuitries.

Preliminaries  Modeling Clock Gating as a Satisfiability Problem -for a net to be a gating signal, either Formula (1) or (1’), but not both, must be true for all input vectors.  SAT is the problem of determining if the variables of a given Boolean formula can be assigned in such a way as to make the formula evaluate to TRUE

 rewrites Formula (1) or (1’), respectively  uses a Boolean SAT solver to solve each of them  If it is unsatisfiable, then Formula (1) or (1’) holds and the net g or its inverse is a valid gating signal for register R.

 For a valid gating signal g verified by Hurst’s algorithm, its gating condition g(x) is usually a subset of the maximal gating condition of the gated register R.  It is possible to enlarge the gating condition in order to increase the gating capability and thus optimize the power consumption.

 Craig’s Interpolation  In this paper, we adopt the interpolation construction technique to derive the gating signals with larger clock gating capability.

Algorithm  Identifying clock gating candidates  Extracting interpolants  Selecting gating signals for power optimization

Identifying clock gating candidates  net-register pair (g, R): g is a net, R is a register  valid gating candidate: the net’s function can be formally proven as a gating condition of the register (Formula 1 or 1’).  millions of net-register pairs: modeling and solving all of them into SAT problems is very time-consuming.  perform logic simulation to filter out invalid net- register pairs before the SAT proofs.

 A net-register pair if both Formulae (1) and (1’) are invalidated by simulation, that is, if there exist two input vectors X 1 and X2 that satisfy Formulae (2) and (2’), it’s invalid.  At the end of simulation, a great portion of the netregister pairs are invalidated and then use SAT engine to prove the rest pairs later.

Extracting interpolants  G-type gating candidate a gating candidate composed by an internal net g and a register R  I-type gating candidate we can construct an interpolant, I, of A and B from their common variables in linear time according to the properties of the interpolation

 I-type gating candidates can enlarge the on-set of g(x) to have better power saving  G-type gating candidates can minimize the gate count of the clock gating logic.  potential timing violation If the candidate on the critical path, the delay of the circuit will increase => discard the candidate

Selecting gating signals for power optimization  P G : the gating probability that is equal to the on-set probability of the gating candidate  N: the number of gated registers  S Ri : the saved power for each of them  C G : the gating power cost resulted from the additional gating logic

 To maximize the power saving Find the gating signals that can gate the most number of registers with the most power savings and the highest gating probabilities Gating power cost should be as low as possible  P G and N in Equation (3) are unavailable

 Use simulation approach to record the hitting probability of a signal as the “estimated gating probability”  Set N to a constant value, just enough to estimate the relative power saving

Implementation  Identifications of the valid gating candidates could be still the timing bottleneck  May suffer the memory explosion from recording all interpolants in the identification processes.  Here presents two techniques to solve both memory and runtime problems.  Brings significant improvement on runtime with tiny decrease in gated clock switches.

 Memory Usage Improvement the additional memory demand comes from the storage of interpolants and their gating logic.  To prevent memory explosion -reduce the number of interpolants -prune away the interpolants with large gating logic

 reduce the number of interpolants merge functionally equivalent interpolants  prune away the interpolants with large gating logic reduce the number of the G-type gating candidates before performing SAT proofs on them picks the G-type gating candidates with the maximum EP G

Runtime Improvement  only keeps the first interpolant more interpolants from the same G-candidate could indeed bring more optimization possibilities =>increase the SAT solving time  In our observation, 90% of the runtime is spent on the SAT proofs in our algorithm  The Memory Usage Improvement technique also helps the runtime improvement

 There are some “hard solving” problems to a SAT solver, which may not be solved in hours  Our algorithm restricts the “backtrack variable” of the SAT solver, MiniSAT [11].  By limiting the backtracking times of a solver, the solver will give up those gating candidates which need more backtracks in the SAT solving.  This is also beneficial to prevent constructing large size of interpolants.

Experimental results

Conclusion  Embedded the interpolation technique to the SAT- based clock gating method with no explicit timing overhead.  Avoid the memory explosion from the interpolation technique.  Have the promising experimental results which perform better or equal power reduction efficiency than Hurst’s SAT-based algorithm.