1. MBSat Satisfiability Program and Heuristics Brief Overview VLSI Testing 304-649B Marc Boulé April 2001 McGill University Electrical and Computer Engineering

2. 1) Introduction The proposed project is the creation of a search based satisfiability solver. Different variable-assignment heuristics will be implemented and evaluated. Satisfiability: “identification of circuit input assignments that satisfy some circuit property” [1]. Time complexity: NP-Complete, therefore believed to requires at least exponential time to compute . SAT is important for circuit verification: an efficient algorithm is beneficial.

3. 2) Applications of SAT Solvers: - logic verification; - path sensitization for test pattern generation; - path sensitization for timing analysis; - path sensitization for delay fault testing.

4. 3) Specifications - input provided in CNF (Conjunctive Normal Form); - multiple clauses ( )( )( )( )…; - multiple literals (L1 + L2 + L3 + L4 …) (nSAT); - output all or at-least-one satisfying vector; - uses backtracking to prune useless portions of search tree; - different heuristics can be selected in the user interface; - ability to stop the program during execution.

5. 4) Benchmarks The SAT Solver will be tested with many different circuits in order to: - verify correct operation of the solver; - evaluate the performance of each heuristic in order to determine which one is the best. The benchmarks consist of combinatorial circuits from the DIMACS Challenge Benchmarks [5] (Center for Discrete Mathematics and Theoretical Computer Science ) as well as some small test circuits.

6. 5) Example case With the following CNF expression [4], the solver should output the following vector: A=0, B=1, C=0, D=1. C1 = ( A + B + C ) ( A + B +  C ) (  A + B +  C ) ( A + C + D ) (  A + C + D ) (  A + C +  D ) (  B +  C +  D ) (  B +  C + D ) MBSAT(C1) = { A=0, B=1, C=0, D=1 }

7. 6) How to use a SAT Solver The program will try to find one(all) PI assignment(s) so that the CNF expression evaluates to 1. What if the desired operation is for the circuit output to be evaluated to 1? Ex: not gate (show all satisfying vectors). C2 = ( A + B ) (  A +  B ) MBSAT(C2) = { A=1, B=0 }  { A=0, B=1 }. However the condition A=1 produces a 0 output. The circuit was not satisfied properly. C3 = ( A + B ) (  A +  B ) ( B ) MBSAT(C3) = { A=0, B=1 }. Correct result.

8. 7) Description of heuristics The next variable to be assigned a logical value is Heuristic A: selected at random from all the unassigned variables. Heuristic B: the unassigned variable that shows up in the greatest number of clauses. Heuristic C: an unassigned variable from the narrowest clause. The narrowest clause is the one with the least number of unassigned variables. Heuristic D: determined by a combination of heuristics B and C. If a clause exists with only one unassigned literal, that variable is chosen. Otherwise, the procedure from heuristic B is used.

9. 8) MBSat algorithm Procedure MBSat(  ) If a clause from  is 0, return unsatisfiable If all clauses from  are 1, return satisfiable Select next unassigned variable depending on the selected heuristic If MBSat(  | selected_variable = true) is satisfiable, return satisfiable Else return MBSat(  | selected_variable = false) Note:  is the clause database.

10. 9) Results The following table shows the average number of search nodes needed to satisfy five different circuits. Circuits have between 35 to 43 variables and 40 to 77 clauses. Search nodes (avg.) Heuristic A>120 000 000 Heuristic B6 323 612 Heuristic C324 438 Heuristic D3 509 402

11. 10) Conclusion Four heuristics were compared and evaluated: heuristic C seems to be the best one. The MBSat program successfully reported satisfiability of all circuits (except for timeout in heuristic A). However, MBSat is too slow to be of practical use for now… 11) Future Work and Improvements - Caching solutions to be reused in other portions of search; - Conflict analysis and implication database; - Stronger preprocessing phase.

12. 12) References [1] J.P.M. Silva, Search Algorithms for Satisfiability Problems in Combinational Switching Circuits, Ph.D. thesis, University of Michigan, 1995. [2] Z. Zilic, VLSI Testing: ATPG By Satisfiability, Course handouts, McGill University, 2001. [3] J.P.M. Silva and K.A. Sakallah, GRASP-A New Search Algorithm for Satisfiability, University of Michigan, 1996. [4] J.P.M. Silva, Boolean Satisfiability Algorithms and Applications in Electronic Design, Tutorial, presented at the Conference on Computer-Aided Verification (CAV), July 2000. [5] Center for Discrete Mathematics and Theoretical Computer Science, “DIMACS Challenge Benchmarks”, ftp://dimacs.rutgers.edu /pub/challenge/sat/benchmarks/cnf/.