CSE 242A Integrated Circuit Layout Automation Lecture: Global Routing Winter 2009 Chung-Kuan Cheng.

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Presentation transcript:

CSE 242A Integrated Circuit Layout Automation Lecture: Global Routing Winter 2009 Chung-Kuan Cheng

Outline Menu Multi-Commodity Flow Top-Down Approach Steiner Tree

Global Routing Menu

Global Routing MCF LP & Duality

Net Ordering

Global Routing Top-Down Approach

T(1)…T(4) T(5)…T(6) T(7)…T(10) T(11) P1 P2 P1P2 P1P2 P3 P1P2 P3 P4

Linear Programming H1 V1 H2 V2

Steiner tree

Maze Routing Breadth First Search: Map memory reduction S S A sequence that guarantees the predecessor is different from its successor. # states: 1, 2, Empty, Filled, 1, 2, 3

Speed-up Limit to a bounding box * 120% Start from two ends Expand from the corners farthest from the center Expand the frontier closer to the target first s t

Depth First Search Line probe

A * router s i t

Ripup and Reroute Net sequence ordering Penalty function on overlapping Route around existing wires Plowing or compaction Topological routing A B C

Ripup and reroute with cost driven router

Overlap Model

Hybrid Router

River Routing Net Ordering For each pin (circular order) If it is a starting pin, push Else if is ending pin, pop into a queue. Route nets to follow contour

Planar Routing Power & Ground Distribution Find a cut line that separates the chip into two regions Obj: min tree length P + treelength G P G G P P G

Gate Matrix A B A B Vdd A 6 B 7 8A B 9 10 Z

AB C Z

Cell Generation Vdd AB C D A B CD Z A B C D Z A B C D Z

Z D D1 1 22CC Z A 4 A 4 B 3 B 3

Find an Euler path on graph G & its dual with same sequence of labels Given serial & parallel graph, the operation is commutative

Compaction S t ‘

Compaction with Wire Jogging

Compression ridge 45 degree path