New Technological Capabilities at CNM25 th RD50 Workshop. CERN, November 19th-21th, 2014 Centro Nacional de MicroelectrónicaInstituto de Microelectrónica.

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New Technological Capabilities at CNM25 th RD50 Workshop. CERN, November 19th-21th, 2014 Centro Nacional de MicroelectrónicaInstituto de Microelectrónica de Barcelona New Technological Capabilities at CNM New Technological Capabilities at CNM David Flores, Pablo Fernández-Martínez, Virginia Greco, Daniela Bassignana, Victor Benitez, Salvador Hidalgo, Giulio Pellegrini, David Quirion, Miguel Ullán Instituto de Microelectrónica de Barcelona (IMB) Centro Nacional de Microelectrónica (CNM-CSIC) Barcelona, Spain

New Technological Capabilities at CNM25 th RD50 Workshop. CERN, November 19th-21th, 2014 Centro Nacional de MicroelectrónicaInstituto de Microelectrónica de Barcelona Outline o Available Technologies in 4” and 6” Developments o Automated Layout Generation o Reverse Engineering Analysis Procedures o Automatic Electrical Characterization

New Technological Capabilities at CNM25 th RD50 Workshop. CERN, November 19th-21th, 2014 Centro Nacional de MicroelectrónicaInstituto de Microelectrónica de Barcelona Name Geom.Substr. Double Metal Thikness (μm) Double Side Wafer Size DC Detectors (Nuclear app.) PlanarNYes Yes (>200 μm)4” DC Detectors (HEP) PlanarN/PYes Yes (>200 μm)4” (6”) AC Microstrips (HEP) PlanarN/PYes Yes (>200 μm)4” (6”) LGAD PlanarPYes Yes (>200 μm)4” (6”) 3D Double Side Detectors 3DN/PYes Yes (>200 μm)4” U3DTHIN 3DNYes5-300No4” Microdosimeter 3DNNo5-300No4” Fan-in Planar-Yes No4” (6”) Technology Status

New Technological Capabilities at CNM25 th RD50 Workshop. CERN, November 19th-21th, 2014 Centro Nacional de MicroelectrónicaInstituto de Microelectrónica de Barcelona 6 inch Technological Process First PiN Diodes on 6 Inches Wafers

New Technological Capabilities at CNM25 th RD50 Workshop. CERN, November 19th-21th, 2014 Centro Nacional de MicroelectrónicaInstituto de Microelectrónica de Barcelona 6 inch Technological Process o First Results: Good electrical performance (leakage, full depletion, etc) Comparable to 4 inch technology PiN diodes

New Technological Capabilities at CNM25 th RD50 Workshop. CERN, November 19th-21th, 2014 Centro Nacional de MicroelectrónicaInstituto de Microelectrónica de Barcelona 6 inch Technological Process o Photolithography with Stepper: All layers designed in one single stepper crystal. Standard in CMOS technologies. Minimum resolution 0.25 µm Contact masks can also be used to produce large size (whole wafer) detectors. Channel Stopper P-DiffWindow Metal Passivation 6700um 5180um

New Technological Capabilities at CNM25 th RD50 Workshop. CERN, November 19th-21th, 2014 Centro Nacional de MicroelectrónicaInstituto de Microelectrónica de Barcelona Automatic Layout Generation o Fast and efficient automatized layout generation with Glade/Python: Freeware IC layout editor: Glade (Gds, Lef and Def Editor) by Peardrop Design Systems capable of reading GDS2, OASIS, LEF and DEF plus a few other formats. Currently available for Windows, Linux, Mac OS X and Solaris. Glade is extendable using Python scripting and parameterized cells (Pcells). We can design complex layout using a complete library of simple parameterized functions. o Full sensor layout generation: Strip rows generation Stereo angle Bonding pads Bias resistors Bias and guard rings

New Technological Capabilities at CNM25 th RD50 Workshop. CERN, November 19th-21th, 2014 Centro Nacional de MicroelectrónicaInstituto de Microelectrónica de Barcelona Reverse Engineering on Microelectronic Devices o The Reverse Engineering Group was created by the Physical Characterization and the Design & CAD staff with a high skills in the integrated circuit analysis and reconstruction. o Expertise in the study of the procedures and the techniques which help to determine the origin of the failures (malfunctions, destruction) on a wide range of electronic devices and circuits, providing the actions to be taken to eliminate the failures and to increase the reliability. o The Reverse Engineering covers from the analysis to the top-down reconstruction of discrete devices and integrated circuits. Process technology characterization Identification of building blocks Layout errors Etc.

New Technological Capabilities at CNM25 th RD50 Workshop. CERN, November 19th-21th, 2014 Centro Nacional de MicroelectrónicaInstituto de Microelectrónica de Barcelona Reverse Engineering o Equipment. Physical Characterization: Focus Ion Beam (FIB) 2 Atomic Force Microscope (AFM) 3 Scanning Electron Microscope (SEM) Automatic polishing machine with multi- sample head Automatic polishing machine with two heads suitable for micro-sections Diamond saw Optical microscopes (micro-measurement, dark field and interferential contrast) Photo microscope Plasma equipment for layer removal Probe system with submicron needles and laser cutting facility Die attach. Wedge and ball bonding facilities.

New Technological Capabilities at CNM25 th RD50 Workshop. CERN, November 19th-21th, 2014 Centro Nacional de MicroelectrónicaInstituto de Microelectrónica de Barcelona o Techniques: Decapsulation Die recovery Microsection Procedure Technology Information High precision mechanical layer removal Bottom-up circuit analysis Top-down circuit analysis Chemical stain of high doped diffusions Memory contents identification FIB-based circuit edition Layout edition and rerouting Security disabling Laser-based circuit edition Reverse Engineering

New Technological Capabilities at CNM25 th RD50 Workshop. CERN, November 19th-21th, 2014 Centro Nacional de MicroelectrónicaInstituto de Microelectrónica de Barcelona Automatic Electrical Characterization o Fast and efficient automatic electrical characterization set-up Automatic 6” wafer probe station with specific test needles adapted to the layout to be measured (Custom probe cards) Agilent E5270B Precision Measurement Mainframe. ±100 V, ±100 mA (minimum resolution of 2 μV, 10 fA). HP4284 LCR Meter. 20 Hz to 1 MHz ±0.01% Control Software for table movement and test and data acquisition. o Automatic measures Electrical Parameters: I(V), C(V), parametric characterization, etc. Technological Characterization: If specific test structures are implemented: sheet resistance, contact resistance, dielectric capacitances, etc.

New Technological Capabilities at CNM25 th RD50 Workshop. CERN, November 19th-21th, 2014 Centro Nacional de MicroelectrónicaInstituto de Microelectrónica de Barcelona Automatic Electrical Characterization Wafer mapping and data analysis with custom developed tools (Matlab & Python)

New Technological Capabilities at CNM25 th RD50 Workshop. CERN, November 19th-21th, 2014 Centro Nacional de MicroelectrónicaInstituto de Microelectrónica de Barcelona Thank you for your attention !!!!