Block Diagram of 4518 Dual BCD Counter The 4518 Dual BCD Counter has two BCD counters. Each counter is similar to the other. Each counter has a master.

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Block Diagram of 4518 Dual BCD Counter The 4518 Dual BCD Counter has two BCD counters. Each counter is similar to the other. Each counter has a master reset (MR) pin and two clock pins. A high on the MR pin resets the BCD counter to zero. There are two clock pins (CP0 and /CP1). The counters increment on the positive edge of CP0 or on the negative edge of /CP1. For the counter to respond to the positive edge of CP0, the /CP1 input must be high. The enabling input of an AND/NAND gate is a positive input. For the counter to respond to the negative edge of /CP1, the CP0 must be low, as it is connected to the AND gate via an inverter. It is this property that allows the clock inputs to be used as ENABLE inputs or HOLD inputs. When CP0 is low, it acts as an ENABLE input for /CP1. When it is high, it acts as a DISABLE input for /CP1 or as a HOLD input for the counter. The counter holds at the last count.

IC5 555 Timer is a monoshot. Pushing S1 makes its out put at pin 3 go high. Since this pin is connected to the MR pins of IC4, both the counters is IC4 are reset. At this time pins 11, 12 (2Q0, 2Q1) are low, hence the output at N3 pin 11 is low and acts as an enable for the first counter in IC4 through CP0 at pin 1.CP0 of the second counter is connected to ground and is always low, and it always enables the counter. The first counter counts from 0 to 9 and repeats. This causes the 1Q3 to give a pulse every 10 clocks. This pulse is fed to the /CP1 of the second counter and so its increments once every 10 clocks. When 30 clocks have elapsed, the 2Q0 and 2Q1 are high. The output at N3 pin 11 goes high and disables it via CP0 of counter 1 at pin 1. Recall that when CP0 is high it disables the clock at /CP1. Hence, we get a pulse that stretches to 30 clocks at pin 11 of N3.

IC3 gets a pulse lasting 30 clocks at pin 1 (CP0 of counter1). It gets a clock at pin 2 from N1 which is representative of a beat. For 30 clocks, the counter 1 counts the number of beats received at pin 2. The counter 2 of IC3 counts the pulses at 1Q3, which occurs every 10 clocks similar to IC4. LED5,4,3,2 is the BCD code for the lower digit and LED9,8,7,6,5 is the BCD code for the upper digit. Hence, when you press S1, an enable pulse for 30 clocks is generated and the heart beats during this period are counted and displayed on the LEDs. Thereafter, the enable signals are inactive and the counters hold their count, till you press S1 again.