Structure of Computer Systems Course 12 RISC architecture

CISC v.s. RISC  CISC – Complex Instruction Set Computer  RISC - Reduced Instruction Set Computer  Historical perspective: at first computers had a limited instruction set because of technological limitations (number of switching elements was limited) at first computers had a limited instruction set because of technological limitations (number of switching elements was limited) as integration technology improved: as integration technology improved: more instructions were included in the set of a computermore instructions were included in the set of a computer more complex operations implemented in instructions => more complex instructionsmore complex operations implemented in instructions => more complex instructions consequences: consequences: CPU became more and more complexCPU became more and more complex CPU became slower (relative to the clock frequency)CPU became slower (relative to the clock frequency) higher CPI and limited clock frequencyhigher CPI and limited clock frequency

CISC  Reasons for complex instruction set computers more powerful instructions more powerful instructions e.g. floating point arithmetic instructionse.g. floating point arithmetic instructions assembly language instructions closer to high level language instructions assembly language instructions closer to high level language instructions e.g. loops, complex conditional jumpse.g. loops, complex conditional jumps more complex addressing modes, as support for complex data structures more complex addressing modes, as support for complex data structures addressing: indexed, based, mixed, scaled, etc.addressing: indexed, based, mixed, scaled, etc.  Benefits: easier programming in assembly language easier programming in assembly language less instructions needed to write an application less instructions needed to write an application easier compilation of high level languages easier compilation of high level languages support for complex data structures support for complex data structures

CISC  Statistical measurements (during the ’70s) which instruction types are more often used in different types of applications ? which instruction types are more often used in different types of applications ? does the programmers use the available complex instructions? does the programmers use the available complex instructions?  Surprising results programmers prefer simple instructions programmers prefer simple instructions complex instructions are used just occasionally, for some very specific operations (e.g. sine, arc tang. log, exponential, etc.) complex instructions are used just occasionally, for some very specific operations (e.g. sine, arc tang. log, exponential, etc.) most of the time the processor is executing simple instructions from a limited set most of the time the processor is executing simple instructions from a limited set  Conclusion: the speed limitation caused by a complex instruction set is not justified the speed limitation caused by a complex instruction set is not justified let’s do things simpler and faster let’s do things simpler and faster

RISC  RISC = Reduced Instruction Set Computer  Principle: sacrifice everything for speed reduce the number of instructions – make CPU simpler reduce the number of instructions – make CPU simpler get rid of complex instructions, which may slow down the CPU get rid of complex instructions, which may slow down the CPU use simple addressing modes – less time spent to compute the address of an operand use simple addressing modes – less time spent to compute the address of an operand limit the number of accesses to the memory limit the number of accesses to the memory if a given operation cannot be executed in one clock period than do not implement it in an instruction if a given operation cannot be executed in one clock period than do not implement it in an instruction extensive use of pipeline architecture – in order to reach CPI=1 (one instruction per clock period) extensive use of pipeline architecture – in order to reach CPI=1 (one instruction per clock period)

RISC - Main features  limited number of instructions in the instruction set: instructions v.s in case of CISC instructions v.s in case of CISC  no complex instructions every instruction executes only one operation every instruction executes only one operation  instructions have fixed format fixed length fixed length few combinations of fields inside the instruction code few combinations of fields inside the instruction code  instructions executed in one clock period (except Load and Store instructions) through intensive use of pipeline architecture through intensive use of pipeline architecture every instruction have the same number of pipeline stages every instruction have the same number of pipeline stages

RISC - Main features  Increased set of general purpose registers e.g registers e.g registers instructions operating with registers are executed in the shortest time instructions operating with registers are executed in the shortest time compensate the lack of instructions operating with the memory compensate the lack of instructions operating with the memory  Use of multiple register sets fast and easy context switch fast and easy context switch use of register set windows use of register set windows

RISC - Main features  Only two instructions operate (have access) to the memory locations: Load – read data from the memory into a register Load – read data from the memory into a register Store – write the data from a register into the memory Store – write the data from a register into the memory Load and Store instructions require two accesses to the memory: Load and Store instructions require two accesses to the memory: one to read the instruction codeone to read the instruction code one to read or write the dataone to read or write the data Load and store instructions are the only instructions which are executed in two clock periods Load and store instructions are the only instructions which are executed in two clock periods all the other instructions from the set are operating with registers or a register and a constant all the other instructions from the set are operating with registers or a register and a constant

RISC - Main features  Hard to write applications in assembly language lack of more powerful instructions and addressing modes lack of more powerful instructions and addressing modes  A program on a RISC is more optimized than the same program written on a CISC only those operations are used which are strictly necessary only those operations are used which are strictly necessary  More effort for programming, less time in execution it is worth to have a greater time spent on programming if at the end the program will be executed many times in a shorter time !? it is worth to have a greater time spent on programming if at the end the program will be executed many times in a shorter time !?

RISC - Main features  The CPU implemented in pure hardware (no microprogramming) instructions are decoded and executed using hardware components instructions are decoded and executed using hardware components higher speed less execution steps higher speed less execution steps  Compilers are more difficult to implement

RISC v.s. CISC ParameterRISCCISC Instruction types SimpleComplex Number of instructions Reduced (30-40) Extended ( ) Duration of an instruction One cycle More cycles (4-120) Instruction format FixedVariable Instruction execution In parallel (pipeline) Sequential Addressing modes SimpleComplex Instructions accessing the memory Two: Load and Store Almost all from the set Register set multipleunique Complexity In compiler In CPU (micro-program)

Performance of RISC v.s. CISC execution time = no_instructions*CPI*Tclk CISC: less long RISC: more 1 short  Hard to tell which is the best  A combination of CISC and RISC may be the solution:  RISC inside, CISC outside – see Pentium processors  complex instructions translated into simple (RISC) instructions

Examples of RISC architectures  Academic implementations: RISC I si II – Berkley University (prof. Patterson, 1980) RISC I si II – Berkley University (prof. Patterson, 1980) MIPS – Univ. Stanford (prof. Hennessy, 1982) MIPS – Univ. Stanford (prof. Hennessy, 1982)  First commercial implementations IBM 801 – compania IBM (1975) IBM 801 – compania IBM (1975) ALPHA – compania DEC ALPHA – compania DEC SPARC – Sun Microsystems (1987) SPARC – Sun Microsystems (1987)  General purpose processors: PowerPC – IBM si Motorola PowerPC – IBM si Motorola ARM architecture ARM architecture

Applications of RISC architectures  Powerful Workstations used for engineering purposes (ex. Sun station) used for engineering purposes (ex. Sun station)  High-end graphical stations used for simulation, animation, etc. used for simulation, animation, etc.  Microcontrollers used for control applications and peripheral devices used for control applications and peripheral devices  Digital signal processors used for signal processing used for signal processing  Mobile devices iPAD, tablet, support for Android systems iPAD, tablet, support for Android systems

RISC architecture examples MIPS  MIPS –  Microprocessor without Interlocking Pipe Stages or  Million Instruction per Second processor: developed by Prof. Hennessy at Stanford University (1982) developed by Prof. Hennessy at Stanford University (1982) a classical pipeline architecture used as reference for teaching basic concepts about computers a classical pipeline architecture used as reference for teaching basic concepts about computers features: features: 32 internal registers32 internal registers reduced instruction setreduced instruction set instructions with fixed length (4 bytes); types: R,J, Iinstructions with fixed length (4 bytes); types: R,J, I 3 operands instructions (source, destination, target)3 operands instructions (source, destination, target) (see a previous course for details)(see a previous course for details)

RISC architecture examples Microcontrollers  Microcontroller all components of a micro-computer system in a single integrated circuit: all components of a micro-computer system in a single integrated circuit: CPUCPU program memoryprogram memory data memorydata memory parallel I/O portsparallel I/O ports serial portsserial ports timers, counterstimers, counters converters: ADC, DAC, PWMconverters: ADC, DAC, PWM watchdogwatchdog used for control applications: used for control applications: monitoringmonitoring feedback controlfeedback control

RISC architecture examples Microcontrollers  Example PIC16Fxx CPU – simple, RISC architecture CPU – simple, RISC architecture Instruction format – fixed, 14 bits/instruction Instruction format – fixed, 14 bits/instruction only 35 instructions only 35 instructions data format: 8 bits data format: 8 bits Internal memory – inside the chip - Harvard architecture – data separated from instructions Internal memory – inside the chip - Harvard architecture – data separated from instructions data memory – 368 bytes SRAM, organized on banksdata memory – 368 bytes SRAM, organized on banks instruction memory – 8kinstructionsinstruction memory – 8kinstructions 256 bytes EEPROM (non-volatile memory)256 bytes EEPROM (non-volatile memory) Interfaces: Interfaces: serial UART and SPIserial UART and SPI Convertors: 10 bits ADC with 8 channel multiplexerConvertors: 10 bits ADC with 8 channel multiplexer 3 timers3 timers parallel portsparallel ports ICD – In Circuit debug functionality ICD – In Circuit debug functionality Package: 28,40 or 44 pins Package: 28,40 or 44 pins Data memory Bank 0 Bank 1 2, 3 0 1Fh Ports area General registers User data area

RISC architecture examples PowerPC  PowerPC = Performance Optimization With Enhanced RISC – Performance Computing designed as a competitor for the Intel X86 processor family designed as a competitor for the Intel X86 processor family developed by Apple, IBM and Motorola (1991) as an open architecture developed by Apple, IBM and Motorola (1991) as an open architecture extension of the IBM’s Power architecture extension of the IBM’s Power architecture RISC and superscalar architecture RISC and superscalar architecture initially intended for PCs, now used for embedded and high performance computers initially intended for PCs, now used for embedded and high performance computers 32 and 64 bit processors 32 and 64 bit processors many versions: PowerPC 601, 602, 604, 620,740, many versions: PowerPC 601, 602, 604, 620,740, computers made with PowerPC: computers made with PowerPC: Macintosh, AppleMacintosh, Apple RS6000, (RISC System 6000), IBMRS6000, (RISC System 6000), IBM embedded computersembedded computers