Vector Multiplication & Color Convolution Team Members Vinay Chinta Sreenivas Patil EECC VLSI Design Projects Dr. Ken Hsu

Goal A VLSI chip capable of 3*3 matrix multiplication or 3*3 digital convolution Design to operate at a frequency suitable for real-time video and image processing applications.

Applications Typically used in applications such as digital copiers where incoming color data needs to undergo unsharp masking for quality color output.  Data is converted into chrominance and luminance channels.  The RGB signals captured by the camera are linearly matrixed and processed for color sensitivity correction using 3*3 matrices.  After this, convolution operation is applied to luminance channel to enhance sharpness.

Multi-functionality Noise reduction, feature extraction, image enhancement, restoration and various other operations performed by linear filter (3*3 convolvers) Providing different kernels or matrices, it can be used for all these image processing operations. The VMCC is the single solution for all these functions.

Modes of Operation Mode 0: Color Matrixing Each output is weighted sum of three input words R, G, B which are the attributes of a single pixel. The output is valid each clock cycle if data is presented to the chip continuously

Color Matrixing

Modes of operation Mode 1: 3*3 2-D convolution Receives image data three pixels at a time in three consecutive pixel times, multiplies the 9 pixel values by the corresponding 9 coefficients stored in the static registers and computes the sum.

2-D Convolution

Functional Block Diagram

Functional Blocks used in the project 10 - bit registers 10 x 10 - bit multipliers 20 - bit adders 10 - bit multiplexers Clock divider (÷3) Shift Register (3 stage 10 bits)

Results for the multiplier Multiplier is the largest combinational block in the design Combinational Area: Non-combinational Area: 0 Total Cell Area: Total Dynamic power : mW Number of cells: 419 Number of gates in critical path: 51

9 Multiplier Design Latency = 6 Clock cycles

9 Multiplier Design Precompiled structure Hardware used 10 - bit registers x 10 - bit multipliers bit adders bit multiplexers - 7

9 Multiplier Design Post - Compiled structure (with low effort)

9 Multiplier Design Post - Compiled structure (with high effort)

Modified Circuit - Block Diagram

3 Multiplier Design Latency = 4 Clock cycles

3 Multiplier Design Precompiled structure Hardware used 10 - bit registers x 10 - bit multipliers bit adders – bit Shift registers - 3 ÷ 3 Clock Dividers- 1

3 Multiplier Design Post - Compiled structure (with high effort)

Real-time operation - with a latency of six clock cycles (in original design) - with a latency of 4 clock cycles (in modified design) The operating speed suitable for real-time NTSC video processing. The MODE input selects either 3*3 matrix multiplication or 2-D convolution. Results Note: This speed has to be divided by factor of 3.

Features Two operations on a single chip. Matrix operations for color processing Convolution for filtering and enhancement. Real-time operation for NTSC signals.

Further Work Design of BIST for the design. Control Interface / Communicator Implementation of High Speed Multiplication and Additions algorithms. Optimize for Higher Speed

References 1. A Pipelined ASIC for Color Matrixing and Convolution, K. Hsu, LJ. D'Luna, H. Yeh, W.A. Cook, G.W. Brown 2. L. J. D'Luna, et al., A Digital Video Signal Post-Processor for Color Image Sensors, Proceedings of CICC Digital integrated circuits : a design perspective, Rabaey,Pearson Education, c W. Wesley Peterson and E. J. Weldon, Jr., Error-Corecting Codes (2nd ed.) 1972, The MIT Press,Cambridge, Massachusetts, 1972, 5. VHDL : Programming By Example, Perry, Douglas L, McGraw-Hill, c x3 Convolver with Run-Time Reconfigurable Vector Multiplier in Atmel AT6000 FPGAs. AT6000 FPGAs. Application Note ( 7. Digital Image Processing, Gonzalez, Rafael C., Woods, E. Richards Introduction To VLSI Circuits And Systems, John P. Uyemura, 1952, J. Wiley, c Fundamentals of digital logic with VHDL design, Brown, Stephen D, McGraw-Hill, c Wikipedia, the free encyclopedia (

Questions ???