© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e Chapter 15 PC Standard Bus Interfaces WK 15

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e Chapter Objectives Describe pin and signal details of typical standard PC buses:  PCI Parallel bus  USB Serial bus Illustrate simple interfaces

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e The need for buses Early PCs had a few parallel ports and serial ports A port was needed for each device interfaced: e.g. printer used a parallel port, e.g. COM1 A standard buss is needed to connect a large number of devices (boards, equipment) made by different manufacturers

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e Hierarchical Bus Structure of the PC Older ISA Bus 8/16 bit data, 20-bit address PCI Bus 32/64 bit data, 32/64-bit address Faster data transfers Faster Devices Plug-In Boards

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e The PCI Parallel Bus PCI: Peripheral Component Interconnect (1991) Latest: PCI-Express The only bus available as standard on Pentium systems 32-bit address bus (provision for 64 bits address) Compatible with both 32-bit and 64-bit data busses Address and data lines are MUXed to reduce size of the board edge connector Clock speed: 33 MHz  66 MHz newer versions The Plug & Play (PnP) Feature made it popular: Using a few registers in a memory on the PCI board, the PC can recognize the board and configure it through software without the user setting jumpers, switches, etc.

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e 32-bit cards (32-bit address & 32-bit data): Pins 1-62 only 64-bit cards (64- bit address (future) & 64-bit data): Pins 1-94 PCI Pin-out (dual-in-line) Data Connections on both sides

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e PCI Burst Bus Cycle Assume 32 bit address & 32 bit data, 33 MHz clock 4 bytes Address & Data MUXed on 32 AD lines Base address Next 4 bytes … Throughput  33 MHz x 4 = 132 M Byte/s 1 bus cycle: transfers 16 bytes of data 33 MHz

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e PCI Configuration Space PCI board 256 Byte Configuration Memory Unit & Vendor IDs Codes assigned by the PCI SIG Board Function, e.g. Network card, VGA card, etc. Base addresses for Both the memory and I/O spaces on the board.

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e D31-D16 of Memory Location 04H D15-D0 of Memory Location 04H

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e The USB Bus The universal serial bus (USB) A very convenient way to interface many I/O device to the personal computer: keyboardskeyboards, mice, flash drives, hard drives, speakers, TV tuners, webcams, etc.flash driveshard drivesspeakersTV tunerswebcams The 4-wire serial bus supports multiple connected devices Supplies power to devices

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e The USB Bus: Some Specs 4-wire serial bus Supports up to 127 device connections Speeds: - USB 1.1 (1994)  1.5 and 12 Mbps - USB 2.0 (2000)  Up to 480 Mbps Cable length limits: - 5 m for full speed interface - 3 m for lower speed versions Power provisions: 5V power supply - Low power loads: 100 mA, e.g. Keyboard - High power loads: 500 mA, e.g. hard disk

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e The Connectors + 5 V 0 V + - Serial Data

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e : Transmit 1 : Receive Line Driver/Receiver IC Noise Suppression IC

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e Data Encoding Digital data is represented as digital signal NRZI code (but here inverts on zero) Signal is not biphase as mentioned in book Signal is unipolar (0 and +5V)

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e (invert on 0) 0 6 th 1 in a row Is replaced by 0 at TX to introduce Sync changes that keep RX synchronized to TX Process is reversed At RX to restore correct transmitted data NRZI encoding & Bit stuffing

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e CRC code USB Error & Flow Control - Stop and Wait - Data and control packets - CRC code for error detection Address Packet ID: Flag and Identifier ACK or Negative ACK Similar to S-Frame in HDLC Similar to ….. Frame in HDLC

© 2006 Pearson Education, Upper Saddle River, NJ All Rights Reserved.Brey: The Intel Microprocessors, 7e PIDNameTypeDescription E1OUTToken Host  function transaction D2ACKHandshakeReceiver accepts packet C3Data0DataData packet (PID even) A5SOFTokenStart of frame 69INToken Function  host transaction 5ANegative ACKHandshakeReceiver does not accept packet 4BData1DataData packet (PID odd) 3CPRESpecialHost preamble 2DSetupTokenSetup command 1EStallTokenStalled To serve as a good preamble flag, it must be a unique pattern: 2 nd 4 bits are complements of 1 st 4 bits! (e.g. E1 = , A5 = )