Input and Output How things get into and out of the CPU.

Slides:



Advertisements
Similar presentations
Accessing I/O Devices Processor Memory BUS I/O Device 1 I/O Device 2.
Advertisements

Buffers & Spoolers J L Martin Think about it… All I/O is relatively slow. For most of us, input by typing is painfully slow. From the CPUs point.
Memory Mapped I/O. What is Memory Mapped I/O? Instead of having special methods for accessing the values to be read or written, just get them from memory.
Input and Output CS 215 Lecture #20.
Avishai Wool lecture Introduction to Systems Programming Lecture 8 Input-Output.
1 Input and Output Patt and Patel Ch Computer System.
Interrupts STOP!!! Do this!!!. CMPE12cGabriel Hugh Elkaim 2 Interrupts Have device tell OS/CPU it is ready Requires hardware to support. OS/CPU can then.
Chapter 8 I/O. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. 8-2 I/O: Connecting to Outside World So far,
Chapter 7 Interupts DMA Channels Context Switching.
Midterm Tuesday October 23 Covers Chapters 3 through 6 - Buses, Clocks, Timing, Edge Triggering, Level Triggering - Cache Memory Systems - Internal Memory.
CMPUT Computer Organization and Architecture I1 CMPUT229 - Fall 2003 Topic8: Input/Output Programming José Nelson Amaral.
1 Today I/O Systems Storage. 2 I/O Devices Many different kinds of I/O devices Software that controls them: device drivers.
Practical Session No. 10 Input &Output (I/O). I/O Devices Input/output (I/O) devices provide the means to interact with the “outside world”. An I/O device.
Copyright ©: Nahrstedt, Angrave, Abdelzaher
Chapter 3 – Computer Hardware Computer Components – Hardware (cont.) Lecture 3.
INPUT-OUTPUT ORGANIZATION
INPUT/OUTPUT ARCHITECTURE By Truc Truong. Input Devices Keyboard Keyboard Mouse Mouse Scanner Scanner CD-Rom CD-Rom Game Controller Game Controller.
Input / Output CS 537 – Introduction to Operating Systems.
MIPS I/O and Interrupt. SPIM I/O and MIPS Interrupts The materials of this lecture can be found in A7-A8 (3 rd Edition) and B7-B8 (4 th Edition).
Input/Output. Input/Output Problems Wide variety of peripherals —Delivering different amounts of data —At different speeds —In different formats All slower.
Chapter 8 Input/Output l I/O basics l Keyboard input l Monitor output l Interrupt driven I/O l DMA.
CHAPTER 5 I/O PRINCIPLE Understand the principles of System Bus
Computer Hardware and Software Jinchang Wang. Hardware vs. Software Hardware is something tangible. Computer hardware includes electronic circuitry and.
Input and Output Computer Organization and Assembly Language: Module 9.
Interrupts and DMA CSCI The Role of the Operating System in Performing I/O Two main jobs of a computer are: –Processing –Performing I/O manage and.
© Janice Regan, CMPT 300, May CMPT 300 Introduction to Operating Systems Principles of I/0 hardware.
CS 342 – Operating Systems Spring 2003 © Ibrahim Korpeoglu Bilkent University1 Input/Output CS 342 – Operating Systems Ibrahim Korpeoglu Bilkent University.
Chapter 8 I/O. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. 8-2 I/O: Connecting to Outside World So far,
MIPS I/O and Interrupt. .data val1:.float 0.6 val2:.float 0.8 msg_done:.asciiz "done\n".text.globl main main: li.s $f0, mfc1 $a0, $f0 jal calsqrt.
Interrupts By Ryan Morris. Overview ● I/O Paradigm ● Synchronization ● Polling ● Control and Status Registers ● Interrupt Driven I/O ● Importance of Interrupts.
Dr Mohamed Menacer College of Computer Science and Engineering Taibah University CE-321: Computer.
Accessing I/O Devices Processor Memory BUS I/O Device 1 I/O Device 2.
13-Nov-15 (1) CSC Computer Organization Lecture 7: Input/Output Organization.
CH10 Input/Output DDDData Transfer EEEExternal Devices IIII/O Modules PPPProgrammed I/O IIIInterrupt-Driven I/O DDDDirect Memory.
Interrupt driven I/O. MIPS RISC Exception Mechanism The processor operates in The processor operates in user mode user mode kernel mode kernel mode Access.
MIPS I/O and Interrupt.
Chapter 13 – I/O Systems (Pgs ). Devices  Two conflicting properties A. Growing uniformity in interfaces (both h/w and s/w): e.g., USB, TWAIN.
Adapted from Computer Organization and Design, Patterson & Hennessy ECE232: Hardware Organization and Design Part 17: Input/Output Chapter 6
1 Lecture 1: Computer System Structures We go over the aspects of computer architecture relevant to OS design  overview  input and output (I/O) organization.
Computer Architecture Lecture – 4.  Discussed individual functional units of the computer.  But to form a fully computational unit, they must be connected.
Lecture on Central Process Unit (CPU)
Input/Output Problems Wide variety of peripherals —Delivering different amounts of data —At different speeds —In different formats All slower than CPU.
IT3002 Computer Architecture
Interrupt driven I/O Computer Organization and Assembly Language: Module 12.
Processor Memory Processor-memory bus I/O Device Bus Adapter I/O Device I/O Device Bus Adapter I/O Device I/O Device Expansion bus I/O Bus.
Input Output Techniques Programmed Interrupt driven Direct Memory Access (DMA)
بسم الله الرحمن الرحيم MEMORY AND I/O.
1 Device Controller I/O units typically consist of A mechanical component: the device itself An electronic component: the device controller or adapter.
Interrupts and Exception Handling. Execution We are quite aware of the Fetch, Execute process of the control unit of the CPU –Fetch and instruction as.
10/15: Lecture Topics Input/Output –Types of I/O Devices –How devices communicate with the rest of the system communicating with the processor communicating.
Von Neumann Machines. 3 The Von Neumann Architecture Model for designing and building computers, based on the following three characteristics: 1)The.
Chapter 8 Input/Output An Hong 2015 Fall School of Computer Science and Technology Lecture on Introduction to.
Practical Session 11 Computer Architecture and Assembly Language Input &Output (I/O)
Computer System Structures
Chapter 8 I/O.
Input/Output.
Chapter 8 I/O.
Chapter 8 I/O.
Operating Systems Chapter 5: Input/Output Management
Chapter 8 I/O.
Computer Architecture and Assembly Language
Interrupts and Exception Handling
MIPS I/O and Interrupt.
Chapter 8 I/O.
Interrupts and Exception Handling
Presentation transcript:

Input and Output How things get into and out of the CPU

CMPE12cCyrus Bazeghi 2 Computer System

CMPE12cCyrus Bazeghi 3 I/O Devices Keyboard User presses ‘A’ key -> ‘a’ ASCII code is 0x61 Keyboard sends this on wires 1 for start, 8-bits of data, 0 for stop ‘a’ is: Buffer at computer catches these bits

CMPE12cCyrus Bazeghi 4 Displays Character display works with the reverse process (sort of) Most displays are “bit mapped” I/O Devices Printers Just like a display but now being “printed” to paper, not a screen. Again, most printers are now “bit mapped” verses character.

CMPE12cCyrus Bazeghi 5 I/O Devices Hard Disk A spinning disk (4600, 5200, 7200, RPM) 2 – 240 GB and growing FAST Magnetic and read/write (like tape) Both sides Usually a stack of platters Disk access Electronic speeds are in the nanoseconds (10-9 sec) Disk speeds are in the milliseconds (10-3 sec) Why use a disk? QueuingSeekRotationTransfer Depends10ms 1ms

CMPE12cCyrus Bazeghi 6 I/O Devices Questions How does CPU ask for a char to be printed? Which printer? Which display? Who’s? When is printer ready for the next char? When does keyboard have the next char? What about the million times slower?

CMPE12cCyrus Bazeghi 7 MAL I/O putc $s0 is # address of char is in $s0 lb $4, ($s0)# $4 char to be printed addi $2, $0, 11# this syscall is like: syscall# jal operating_system_function getc $s0 is addi $2, $0, 12# this syscall is like: syscall# jal operating_system_function # returns with char read in $2

CMPE12cCyrus Bazeghi 8 MAL I/O Don’t use “jal” because OS doesn’t trust user to provide the correct address Want to switch into OS mode, where more things are allowed Allowed by what? OS catches “syscall” and uses value in $2 to determine what to do OS will not allow (or should not) Users to read each other’s keyboards Users to send infinite jobs to printers (well, actually…)

CMPE12cCyrus Bazeghi 9 MAL I/O How does the OS do I/O? What instructions cause an I/O? Could have special instructions Hard to anticipate all possibilities Solutions overload load and store Memory-mapped I/O

CMPE12cCyrus Bazeghi 10 Memory Mapped IO Idea is to place devices other than RAM chips at physical address locations. This way to access IO devices you use the same load and store instructions.

CMPE12cCyrus Bazeghi 11 Memory Mapped I/O Design hardware and software to recognize certain addresses Real Memory - RAM 0x xffff0000 0xffff0008 0xffff0010 From keyboard To display Set some labels and use those to access devices keyboardDataequ0xffff0008 displayDataequ0xffff0010

CMPE12cCyrus Bazeghi 12 Memory Mapped I/O CPUMEM Keyboard Buffer 0xffff0008 Display Buffer 0xffff0010 Devices on bus watch for their address getc operating_system_function_12:# getc char and put it in $2 lw$2, KeyboardData “return from syscall” putc operating_system_function_11:# putc char, where char is in $4 sw$2, DisplayData “return from syscall” But is there a new char to read? But is the display done with the last char? System bus

CMPE12cCyrus Bazeghi 13 Device Status Need I/O device status to coordinate Set up some more labels KeyboardStatusequ0xffff000c DisplayStatusequ0xffff0014 Assume Status is word where MSB==1 means ready. 0x xffff0000 0xffff0008 0xffff000c DATA from keyboard STATUS from keyboard 0xffff0010 0xffff0014 DATA to Display STATUS from Display Real Memory - RAM

CMPE12cCyrus Bazeghi 14 Device Status GETC Operating_system_function_12:# getc char and put it in $2 WaitLoop12: lw $14, KeybaordStatus bgez $14, WaitLoop12# keep waiting if $14 non-negative lw $2, KeyboardData# same as before “return from syscall” PUTC Operating_system_function_11:# putc char, where char is in $4 WaitLoop12: lw $14, DisplayStatus bgez $14, WaitLoop11# keep waiting if $14 non-negative sw $4, DisplayData# same as before “return from syscall” MAL OS calls

CMPE12cCyrus Bazeghi 15 Device Status Polling (non-interrupt) I/O GETCHAR GETCHAR: LDAASCSR; status register ANDA#$20; rdrf bit mask BEQGETCHAR; loop if rdrf = 0 LDAASCDR; read data RTS OUTCHAR OUTCHAR: LDABSCSR; load sci status register BITB#$80; tdre bit BEQOUTCHAR; loop intil tdre = 0 STAASCDR; write character to port RTS HC11

CMPE12cCyrus Bazeghi 16 Device Status How much time is spent spinning? A putc or getc is less than 10 instructions, or 10ns on a modern processor Mechanical devices take milliseconds Almost all time is spent spinning Must do useful work while waiting Periodically poll devices and send characters when ready

CMPE12cCyrus Bazeghi 17 Polling I/O The OS must check regularly (poll) for ready devices Perhaps once a millisecond If ready, then OS services device Keyboard: transfer character and put on queue Display: transmit character to the graphics HW Problems: How often to poll? How does the OS code get run? What happens to the user program? Is there a better solution?