Lecture 8 Shelving in Superscalar Processors (Part 1) Advanced Computer Architecture Lecture 8 Shelving in Superscalar Processors (Part 1) Give qualifications of instructors: DAP teaching computer architecture at Berkeley since 1977 Co-athor of textbook used in class Best known for being one of pioneers of RISC currently author of article on future of microprocessors in SciAm Sept 1995 RY took 152 as student, TAed 152,instructor in 152 undergrad and grad work at Berkeley joined NextGen to design fact 80x86 microprocessors one of architects of UltraSPARC fastest SPARC mper shipping this Fall

Direct Issue

The principle of shelving: Indirect Issue

Design Space of Shelving

Scope of Shelving

Layout of Shelving Buffers

Implementation of Shelving Buffer

Basic Variants of Shelving Buffers

Using a Combined Buffer for Shelving, Renaming, and Reordering

Number of Shelving Buffer Entries

Number of read and write ports how many instructions may be written into (input ports) or read out from (output parts) a particular shelving buffer in a cycle depend on individual, group, or central reservation stations

Shelving: Operand Fetch Policy

Operand Fetch Policies

Operand fetch during instruction issue Reg. file

Operand fetch during instruction dispatch Reg. file