ECE 331 – Digital System Design Single-bit Adder Circuits and Adder Circuits in VHDL (Lecture #12) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design, 6 th Edition, by Roth and Kinney, and were used with permission from Cengage Learning.

Fall 2010ECE Digital System Design2 The Half Adder (HA)

Fall 2010ECE Digital System Design3 The Half Adder Sum Carry Sum

Fall 2010ECE Digital System Design4 The Half Adder ABSumCarry Truth Table

Fall 2010ECE Digital System Design5 The Half Adder Given the truth table on the previous slide, 1. Derive the Boolean expressions for the sum and carry. 2. Draw the corresponding circuit diagram.

Fall 2010ECE Digital System Design6 The Full Adder (FA)

Fall 2010ECE Digital System Design7 The Full Adder Carry-out Sum Carry-in

Fall 2010ECE Digital System Design8 The Full Adder ABC in SumC out Truth Table

Fall 2010ECE Digital System Design9 The Full Adder Given the truth table on the previous slide, 1. Derive the Boolean expressions for the sum and carry-out. 2. Draw the corresponding circuit diagram.

Fall 2010ECE Digital System Design10 The Full Adder Design the Full Adder hierarchically, using 2 Half Adders 1 OR gate

Fall 2010ECE Digital System Design11 VHDL

Fall 2010ECE Digital System Design12 Components Components permit hierarchical, or top-down, design.  Used in the structural VHDL model. Components, like functions in C, describe sub-circuits that can be used (and reused) in a top-level design. Specify the interface to the sub-circuit.  Component Declaration  Using the same syntax as the Entity statement Define the behavior of the sub-circuit  Component Definition  Using an Architecture statement

Fall 2010ECE Digital System Design13 Components The architecture statement for each component may be included in the same VHDL file as the top-level design, or in a separate file. If included in the same file, it is analogous to defining a function in the same file as the “main” in a C program. If included in a separate file, it must be compiled prior to the compilation of the top-level design.

Fall 2010ECE Digital System Design14 Components Component Declaration Component Instantiation COMPONENT PORT ( : modetype ) ; END COMPONENT ; : PORT MAP ( => ) ; : PORT MAP ( ) ; named association positional association

Fall 2010ECE Digital System Design15 Packages Packages (and libraries) allow frequently used components and functions to be “centrally” located. Component declarations are included in a package file, rather than in the upper-level design file. The corresponding component definitions are included in separate files.  The compiled component definitions are typically included in the same library as the package file. When the package file is compiled the package is created in the working directory.

Fall 2010ECE Digital System Design16 Packages Package Declaration Package Instantiation PACKAGE IS ; END ; LIBRARY work ; USE work..all ;

Fall 2010ECE Digital System Design17 Adder Circuits in VHDL

Fall 2010ECE Digital System Design18 The Half Adder in VHDL A B Sum Carry Half Adder Entity Architecture

Fall 2010ECE Digital System Design19 The Half Adder in VHDL (Behavioral Model – Boolean expressions)

Fall 2010ECE Digital System Design20 The Half Adder in VHDL (Behavioral Model – Truth Table)

Fall 2010ECE Digital System Design21 The Full Adder in VHDL Entity Architecture A B Sum Cout Full Adder Cin

Fall 2010ECE Digital System Design22 The Full Adder in VHDL (Behavioral Model – Boolean expressions)

Fall 2010ECE Digital System Design23 The Full Adder in VHDL (Structural Model) Half Adder (ha1) Half Adder (ha2) A B Cin Sum Cout input ports Entity output ports Architecture signals s1 c1 c2

Fall The Full Adder in VHDL (Structural Model)

Fall 2010ECE Digital System Design25 The Full Adder in VHDL LIBRARY ieee ; USE ieee.std_logic_1164.all ; PACKAGE halfadd_package IS COMPONENT half_adder PORT ( A, B: IN STD_LOGIC ; Sum, Cout: OUT STD_LOGIC ) ; END COMPONENT ; END halfadd_package ; (The Package File)

Fall 2010ECE Digital System Design26 The Full Adder in VHDL LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE work.halfadd_package.all ; ENTITY full_adder IS PORT ( Cin, A, B : IN STD_LOGIC ; Sum, Cout : OUT STD_LOGIC ) ; END full_adder ; ARCHITECTURE Structure OF full_adder IS SIGNAL s1, c1, c2:STD_LOGIC ; BEGIN ha1 : half_adder PORT MAP ( A => A, B => B, Sum => s1, Cout => c1 ) ; ha2 : half_adder PORT MAP ( s1, Cin, Sum, c2 ); Cout <= c1 OR c2 ; END Structure ; (The Design File)

Fall 2010ECE Digital System Design27 Questions?