Memory Management 2 Tanenbaum Ch. 3 Silberschatz Ch. 8,9

cs431-cotter2 Paging implementation issues: The mapping from virtual address to physical address must be fast. If the virtual address space is large, the page table will be large. Speeding Up Paging Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved

cs431-cotter3 Translation look-aside Buffers (TLB) Also known as associative registers High speed cache used to store recent page accesses Supports parallel search algorithm page # | frame #

cs431-cotter4 Figure A TLB to speed up paging. Translation Lookaside Buffers Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved

cs431-cotter5 Paging Hardware with TLB CPU Physical Memory Page Table f p { pd d logical address physical address TLB

cs431-cotter6 Paging Hardware with TLB CPU Physical Memory Page Table f p { pd df logical address physical address TLB

cs431-cotter7 Paging Hardware with TLB CPU Physical Memory Page Table f p { pd df logical address physical address TLB

cs431-cotter8 TLB Performance Frequency with which address is found in TLB is known as hit ratio –Hit ratio depends on many things, including # of TLBs –higher is better...

cs431-cotter9 TLB Performance Frequency with which address is found in TLB is known as hit ratio –Hit ratio depends on many things, including # of TLBs –higher is better... Example: –Hit ratio = 80%, TLB access time = 2 ns, memory access = 20 ns.

cs431-cotter10 TLB Performance Frequency with which address is found in TLB is known as hit ratio –Hit ratio depends on many things, including # of TLBs –higher is better... Example: –Hit ratio = 80%, TLB access time = 2 ns, memory access = 20 ns. 80% * 22 ns + 20% * 42 ns = 26 ns effective access time

cs431-cotter11 TLB Performance Frequency with which address is found in TLB is known as hit ratio –Hit ratio depends on many things, including # of TLBs –higher is better... Example: –Hit ratio = 80%, TLB access time = 2 ns, memory access = 20 ns. –80% * 22 ns + 20% * 42 ns = 26 ns effective access time –Hit ratio = 98%, TLB access time = 2 ns, memory access = 20 ns. –98% * 22 ns + 2% * 42 ns = 22.4 ns effective access time

cs431-cotter12 Memory Protection with Paging Every process has its own paging table Each paging table entry has a protection bit –valid-invalid bit –Page is valid if process is allowed to access the associated page. –Invalid if not. Might also include bits for write and execute

cs431-cotter13 Memory Protection with Paging Every process has its own paging table Each paging table entry has a protection bit –valid-invalid bit –Page is valid if process is allowed to access the associated page. –Invalid if not. Might also include bits for write and execute Problem: Paging tables can become very large

cs431-cotter14 Multi-level Paging Break the page number into two parts First paging number (p1) accesses outer table Second paging number (p2) identifies inner table (d) identifies the displacement within the page P1P2d

cs431-cotter15 Multi-level Paging Break the page number into two parts First paging number (p1) accesses outer table Second paging number (p2) identifies inner table (d) identifies the displacement within the page p1 p2 d outer-page table inner-page table physical memory p1 p2 P1P2d d

cs431-cotter16 Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved Multilevel Page Tables Figure (a) A 32-bit address with two page table fields. (b) Two-level page tables.

cs431-cotter17 Performance of Multi-level Paging Each memory access now requires 3 (or more) accesses to physical memory. Benefit of TLBs now even more important. Hit ratio even more important

cs431-cotter18 Performance of Multi-level Paging Each memory access now requires 3 (or more) accesses to physical memory. Benefit of TLBs now even more important. Hit ratio even more important Example: 4 level paging (Motorola) –Hit ratio = 98%, TLB access time = 2 ns, memory access = 20 ns. 98% * 22 ns + 2% * 102 ns = 23.6 ns effective access time

cs431-cotter19 Inverted Page Table One Page table per system CPU Physical Memory di pid p logical address physical address pid p d i

cs431-cotter20 Inverted Page Table One Page table per system Uses hash table to access table CPU Physical Memory di pid p logical address physical address pid p d i

cs431-cotter21 Figure Comparison of a traditional page table with an inverted page table. Inverted Page Tables Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved

cs431-cotter22 Theories of Program Behavior All replacement algorithms try to predict the future All replacement algorithms have a theory of how programs behave –Theory is used to predict future behavior of the process (when the page will be referenced) –Then replace page that will not be used for the longest time.

cs431-cotter23 Optimal page replacement algorithm Random page replacement Not recently used page replacement First-In, First-Out page replacement Second chance page replacement Clock page replacement Least recently used page replacement Working set page replacement WSClock page replacement Page Replacement Algorithms Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved

cs431-cotter24 Random Page-replacement Randomly pick a page to replace Theory: Since we can't predict the future, why try. Implementation is easy Performance: poor

cs431-cotter25 FIFO Page-replacement Algorithm Maintain a queue of pages. Always replace the page that has been in memory the longest Theory: Pages are used for a while and then not used. Implementation is very easy Performance is poor... –old pages are still used

cs431-cotter26 Expected Page Fault Behavior # of Page Faults Number of Frames

FIFO Example – Program - 5 pages, 3 frames of Memory allocated

 9 faults FIFO Example – Program - 5 pages, 3 frames of Memory allocated

 10 faults FIFO Example – Program - 5 pages, 4 frames of Memory allocated

cs431-cotter30 Belady's Anomaly # of Page Faults Number of Frames

cs431-cotter31 Figure Operation of second chance. (a) Pages sorted in FIFO order. (b) Page list if a page fault occurs at time 20 and A has its R bit set. The numbers above the pages are their load times. Second Chance Algorithm Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved

cs431-cotter32 Figure The clock page replacement algorithm. The Clock Page Replacement Algorithm Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved

cs431-cotter33 Working Set The set of pages that a process is “currently referencing” Based on concept of Locality of Reference Generally modeled using a Working Set Window which is a time period during which the range of page references are monitored. –May be a specific time interval (# of instructions) –May be a specific number of page references Example - Sort 3 different arrays.

cs431-cotter34 Working Set Evolution Size of the working set Time Stable Working Set Stable Working Set Stable Working Set Transition

cs431-cotter35 Figure The working set is the set of pages used by the k most recent memory references. The function w(k, t) is the size of the working set at time t. Working Set Page Replacement (1) Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved

cs431-cotter36 Figure The working set algorithm. Working Set Page Replacement (2) Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved

cs431-cotter37 Thrashing If process does not have "enough" pages, page fault rate goes up. This leads to: –low CPU Utilization –CPU thinks it needs to increase the degree of multiprogramming –Another process is added –More processes reduces the number of frames available to each process Thrashing occurs when a process is spending more time managing page faults than processing.

cs431-cotter38 Thrashing Diagram thrashing degree of multiprogramming CPU utilization

cs431-cotter39 Thrashing Why does paging work? –locality of reference –Process migrates from one locality to another –Localities may overlap Why does thrashing occur? –  (size of locality) > total memory size Solution! –if thrashing occurs, suspend a process

cs431-cotter40 When the hand comes all the way around to its starting point there are two cases to consider: At least one write has been scheduled. No writes have been scheduled. The WSClock Page Replacement Algorithm (1) Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved

cs431-cotter41 Figure Operation of the WSClock algorithm. (a) and (b) give an example of what happens when R = 1. The WSClock Page Replacement Algorithm (2) Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved

cs431-cotter42 Figure Operation of the WSClock algorithm. (c) and (d) give an example of R = 0. The WSClock Page Replacement Algorithm (3) Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved

cs431-cotter43 Figure Page replacement algorithms discussed in the text. Summary of Page Replacement Algorithms Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved

cs431-cotter44 Summary Translation Look-aside Buffers Multi-level Paging Tables Page Replacement Algorithms Working Sets Page Fault Behavior –Thrashing –Belady’s Anomaly

Questions How are TLBs used to improve main memory performance? What is the effective access time for a system with 2 ns TLBs, 20 ns memory access time, and a hit rate of 98%? Page tables are needed to find physical addresses in paging systems. What is the major disadvantage of paging tables, and how do modern operating systems get around this disadvantage? How much memory would be needed for a 1 MB program using a single level page table (32 bit address space, 4 bytes per page, 4kb pages)? How much would be needed for a 4 level page table? What is Belady's Anomaly? What is a working-set model? How does it help determine the allocation of frames of main memory to active processes? What is thrashing in the context of virtual memory?