Topics: 1. Priority Encoders 2. A question from an exam 3. Addition (if time permits) מבנה המחשב - אביב 2005 תרגול 6#

Correctness of PCP-OR (Q6.1)

Correctness of PCP-OR (cont.) The correctness of the design: Note the design is given for n = 2 k. Prove by induction on k. Basis: k = 1, Trivial (correctness of OR). Hypothesis: Assume correct for all j<k+1. Step: Prove for k=1. Observation: If y[s] = 1, then y[t] = 1 for t >= s.

Correctness of PCP-OR (cont.) Separate into two cases: If the leading one is on the [n/2:n-1]  The leading x values are 0, and hence y[0:n/2-1] = 0 (as should be). y[n/2:n-1] are correct by the induction. If the leading one is on the [0:n/2-1]  All the trailing outputs should be 1(observation). So y[n/2:n-1] = 1. y[0:n/2-1] are correct by the induction.

Non 2 k PCP-OR For this case, we use the padding idea. We pad the number of bits to be a whole power of 2. Question: What should it be padded with? Answer: Doesn’t matter for the PCP-OR.

Delay analysis of PCP-OR d(n) = d(n/2) + 1.  d(n) = log(n). For n  2k, the padding leads to d(n) =  log(n) .

Lower bound for the delay of PCP-OR This type of proof can be extended for PCP-OP for many other op. First we show that all the input bits are non- redundant. Assume there is a redundant bit, then we can make the circuit return wrong result (0 in all bits besides this one). Now we can use cone argument and obtain log(n).

Lower bound for the cost of PCP-OR (Q6.2) Note the design given is of cost O(n logn). Is this optimal? No, a trivial design can lead to linear size implementation. y[0] = x[0] y[j] = OR(y[j-1],x[j]). So every new output requires only one new gate, and the design is correct due to the associativity of the OR operation.

Lower bound for the cost of PCP-OR (cont.) So the lower bound we try to prove is linear. Note that there are no trivial outputs, i.e., no output is constant or equals an input bit (besides y[0]). Moreover, no output y[k] equals any other output y[j] (j  k).  Every output bit is the output of a non-trivial gate, and hence the c(n) =  (n).

Q1 from Exam 2000a Input: x[0:n-1] Output y[0:n-1] Functionality: –Let s[j] = Σ x[k] (k=0..j) –Let t[j] = Σ s[k] (k=0..j) –y[j] = 1 if and only if s[j] and t[j] are even.

Q1 from Exam 2000a (cont.) Note that: –s[0] = x[0]. –s[1] = x[0] + x[1]. –s[2] = x[0] + x[1] + x[2]. –s[3] = x[0] + x[1] + x[2] + x[3]. –t[0] = x[0]. –t[1] = 2x[0] + x[1]. –t[2] = 3x[0] + 2x[1] + x[2]. –t[3] = 4x[0] + 3x[1] + 2x[2] + x[3].

Q1 from Exam 2000a (cont.) Note that: –Parity(s[0]) = XOR(x[0]). –Parity(s[1]) = XOR(x[0] + x[1]). –Parity(s[2]) = XOR(x[0] + x[1] + x[2]). –Parity(s[3]) = XOR(x[0] + x[1] + x[2] + x[3]). –Parity(t[0]) = XOR(x[0]). –Parity(t[1]) = XOR(x[1]). –Parity(t[2]) = XOR(x[0] + x[2]). –Parity(t[3]) = XOR(x[1] + x[3]).

Q1 from Exam 2000a (cont.) y[2k+1] = 1 if and only if: –The XOR of the odd bits is 1. –The XOR of all bits is 1. In order that y[2k] = 1 if and only if: –The XOR of the even bits is 1. –The XOR of all bits is 1.  Conclusion: The XOR of even bits and the XOR of odd bits should be 1.

Q1 from Exam 2000a (cont.) Conclusion2: –We need to calculate the PCP-XOR of the odd bits. –We need to calculate the PCP-XOR of the even bits. –We combine them with AND (and not) gate, for each j. Conclusion3: The circuit is composed of 2 PCP-XOR trees and linear number of gates.

Q1 from Exam 2000a (cont.) So how do we implement (in logarithmic delay and linear time a PCP-XOR tree? Hint: Look at the design of PCP-OP (for any binary OP), you used in fast addition.

Functionality of Adder (Q8.1) An adder gets three inputs A[0:n-1], B[0:n-1], C[0], and returns S[0:n-1], C[n], such that: + + = 2 n C[n]+ Is the functionality of Adder is well defined? In order to prove this, we need to show that for every possible input A,B,C[0] there exists exactly one output S,C[n], that agree with the definition.

Functionality of Adder (cont.) The minimum value A+B+C[0] is 0. The maximum value of A+B+C[0] is 2 n+1 – 1. Any number in this range can be represented by n+1bits, so 2 n C[n]+ are enough to represent every number in this range. The representation is unique, so the result of Adder is unique (and hence well defined).

Lower bounds for Adder (Q8.2) The delay is d(n) =  (log n). The proof is done using cone arguments. Non of the input bits is redundant (trivial). So the cone is cone of 2n+1 bits. The cost is c(n) =  (n). The proof is (again) by examining the outputs. Non of them is trivial. Non of them equals the input.

Lower bounds for Adder (cont.) The cost is c(n) =  (n). The proof is (again) by examining the outputs. Non of them is trivial. Non of them equals the input. Non of them equals the other.  Every output comes from a unique gate, so there must be  (n) gates.