CSCE101 – Database Intro, 4.3 - CPU and Memory October 24, 2006.

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Presentation transcript:

CSCE101 – Database Intro, CPU and Memory October 24, 2006

Database Lab Tables Queries Reports

More on CPU Control Unit, ALU, Registers, Buses Logic - >, =, Word Size Instruction Cycle – –Fetch –Decode –Execute –Store Pipelining

Machine Cycle

Pipelining

Other Methods of Speeding up Processing Interleaving – producing a continuous flow of data from multiple memory banks Bursting – plays on probabilities… retrieval of a block of data or a block of instructions into the cache. Superscalar Architecture – Multicore processors, hyperthreading

Superscalar Architecture

Four Principal Types of Memory Chips File Open…File Save Having enough primary storage (primary memory) is a critical matter. RAM – “256MB SDRAM” ROM CMOS Flash Volatile vs. Non-volatile

More on memory… L1, L2, L3 caches Virtual Memory Paging Revisiting Thrashing

Ports Ports - Serial, Parallel, & SCSI Daisy-chaining More ports – USB and Firewire Why are USB ports so great? –Connecting many devices to one port –Connecting different devices –Hot pluggable –Automatic installation

Ports (Continued) Firewire – data intensive devices MIDI – musical devices IrDA – wireless, infrared short-range Bluetooth – wireless radio short-range Ethernet – LAN linkages Multimedia ports

Expansion Closed vs. Open Architecture Common Expansion Cards – graphics, sound, network, PC Expansion buses (vs. local bus)