Informationsteknologi Friday, October 19, 2007Computer Architecture I - Class 81 Today’s class Digital Logic

Informationsteknologi Friday, October 19, 2007Computer Architecture I - Class 82 Digital circuits Two logical values  Binary 0 (signal between 0 and 1 volt)  Binary 1 (signal between 2 and 5 volts) Gates are small electronic devices that compute various functions of these two- valued signals

Informationsteknologi Friday, October 19, 2007Computer Architecture I - Class 83 Transistor Inverter (NOT Gate) When the input voltage, V in, is below a critical value the transistor turns off and acts like an infinite resistance, so V out is very close to V cc, an externally regulated voltage (typically 5 V) When V in exceeds the critical value the transistor switches on and acts like a wire, causing V out to be pulled down to ground (0 V)

Informationsteknologi Friday, October 19, 2007Computer Architecture I - Class 84 NAND Gate If both V 1 and V 2 are high, both transistors will conduct and V out will be low If either V 1 or V 2 is low the corresponding transistor will turn off and the V out will be high

Informationsteknologi Friday, October 19, 2007Computer Architecture I - Class 85 NOR Gate If either V 1 or V 2 is high the corresponding transistor will turn on and V out will be pulled to ground (0 V) If both V 1 and V 2 are low then V out will remain high

Informationsteknologi Friday, October 19, 2007Computer Architecture I - Class 86 Gates and Boolean Algebra

Informationsteknologi Friday, October 19, 2007Computer Architecture I - Class 87 The Majority Function

Informationsteknologi Friday, October 19, 2007Computer Architecture I - Class 88 Boolean Circuits Write down the truth table for the function Provide inverters to generate the complement (NOT) of each input Draw an AND gate for each term with a 1 in the result column Wire the AND gates to the appropriate inputs Feed the output of all the AND gates into an OR gate

Informationsteknologi Friday, October 19, 2007Computer Architecture I - Class 89 Boolean Function Notation Truth table can get too large for more than 3 or 4 inputs Use a notation that specifies which combinations of inputs produce an output of 1

Informationsteknologi Friday, October 19, 2007Computer Architecture I - Class 810 Using Only NAND and NOR

Informationsteknologi Friday, October 19, 2007Computer Architecture I - Class 811 Circuit Equivalence

Informationsteknologi Friday, October 19, 2007Computer Architecture I - Class 812 Boolean Algebra Identities

Informationsteknologi Friday, October 19, 2007Computer Architecture I - Class 813 Alternative Symbols for Some Gates

Informationsteknologi Friday, October 19, 2007Computer Architecture I - Class 814 Three Circuits for XOR

Informationsteknologi Friday, October 19, 2007Computer Architecture I - Class 815 In-Class Exercise Use a truth table to show that X = (X AND Y) OR (X AND NOT Y) Show how the AND function can be constructed from two NAND gates

Informationsteknologi Friday, October 19, 2007Computer Architecture I - Class 816 Integrated Circuits

Informationsteknologi Friday, October 19, 2007Computer Architecture I - Class 817 Multiplexer

Informationsteknologi Friday, October 19, 2007Computer Architecture I - Class 818 Decoder

Informationsteknologi Friday, October 19, 2007Computer Architecture I - Class 819 Comparator

Informationsteknologi Friday, October 19, 2007Computer Architecture I - Class 820 Shifter

Informationsteknologi Friday, October 19, 2007Computer Architecture I - Class 821 Half Adder (a) (b)

Informationsteknologi Friday, October 19, 2007Computer Architecture I - Class 822 Full Adder

Informationsteknologi Friday, October 19, 2007Computer Architecture I - Class 823 Arithmetic Logic Unit

Informationsteknologi Friday, October 19, 2007Computer Architecture I - Class 824 SR Latch

Informationsteknologi Friday, October 19, 2007Computer Architecture I - Class 825 Clocked SR Latch A clocked SR latch.

Informationsteknologi Friday, October 19, 2007Computer Architecture I - Class 826 Clocked D Latch A clocked D latch.

Informationsteknologi Friday, October 19, 2007Computer Architecture I - Class 827 Flip-Flops

Informationsteknologi Friday, October 19, 2007Computer Architecture I - Class 828 D Flip-Flop

Informationsteknologi Friday, October 19, 2007Computer Architecture I - Class 829 Latch and Flip-Flop Symbols

Informationsteknologi Friday, October 19, 2007Computer Architecture I - Class 830 Octal Flip-Flop (8-Bit Register)

Informationsteknologi Friday, October 19, 2007Computer Architecture I - Class 831 Memory

Informationsteknologi Friday, October 19, 2007Computer Architecture I - Class 832 Buffers (a) A noninverting buffer. (b) Effect of (a) when control is high. (c) Effect of (a) when control is low. (d) An inverting buffer.

Informationsteknologi Friday, October 19, 2007Computer Architecture I - Class Mbit Memory Chips

Informationsteknologi Friday, October 19, 2007Computer Architecture I - Class 834 CPU Chips The logical pinout of a generic CPU. Arrows indicate input signals and output signals. Short diagonal lines indicate that multiple pins are used.

Informationsteknologi Friday, October 19, 2007Computer Architecture I - Class 835 Computer Buses A bus is a common electrical pathway between multiple devices

Informationsteknologi Friday, October 19, 2007Computer Architecture I - Class 836 Masters and Slaves Active devices which can initiate bus transfers are called masters Passive devices which wait for requests are called slaves

Informationsteknologi Friday, October 19, 2007Computer Architecture I - Class 837 The Pentium 4

Informationsteknologi Friday, October 19, 2007Computer Architecture I - Class 838 The Pentium 4’s Logical Pinout Names in upper case are the official Intel names for individual signals. Names in mixed case are groups of related signals or signal descriptions.

Informationsteknologi Friday, October 19, 2007Computer Architecture I - Class 839 Pipelining on the Pentium 4’s Memory Bus

Informationsteknologi Friday, October 19, 2007Computer Architecture I - Class 840 Pentium 4 Bus Structure

Informationsteknologi Friday, October 19, 2007Computer Architecture I - Class 841 PCI Bus Arbitration The PCI bus uses a centralized bus arbiter.

Informationsteknologi Friday, October 19, 2007Computer Architecture I - Class 842 The Universal Serial Bus PCI bus is too expensive for low speed I/O devices (e.g. keyboard, mouse) USB was designed by 7 companies as a better way to attach low speed I/O devices to a computer

Informationsteknologi Friday, October 19, 2007Computer Architecture I - Class 843 USB Goals Users must not have to set switches or jumpers Users must not have to open the case Only one kind of cable, for all devices Devices should get their power from the cable Up to 127 devices should be attachable to a single computer System should support real-time devices Devices should be installable while the computer is running No reboot should be needed after installing a new device Devices should be inexpensive to manufacture