Latch/Register Scheduling Under Process Variation Aaron Hurst EE 290a, Spring 2005

Review  Latch timing is more tolerant to post- manufacturing process variation D1D1 ok D2D ? fail T=5 D 1 = D 2 = {4,6}, P (each) = 50% D2D2 R1R1 R3R3 D1D1 ? d=1  22 D1D1 D2D2

Review  No edge-triggered schedule can match level- sensitive yield Optimal schedule varies from manufactured device to device We don’t know at design-time where to schedule latch points  Can not be quantified with static timing analysis Effect is lost in worst-case analysis Either it will or will not fail

Goal 1. Measure the yield of a scheduled design (verification problem) 2. Find the latch schedule that maximizes yield (optimization problem) General Problem  For each latch, find   and   to maximize yield Single duty clock Problem  Find a global w, and a   for each latch (where   =   + w) to maximize yield L      

Verification  Two methods for verifying a latch schedule 1. Iterative [SMO 90]  Start by assuming the earliest departure times  Find the actual arrivals at latch inputs  Iterate until a fixpoint is reached 2. Structural [Szymanski 92]  Construct a constraint graph  Search for negative cycles in the graph  Can be extended into statistical domain [Zhou 04]

Verification – Iterative Method  Iteration based upon well-researched foundation Statistical timing analysis vs. negative cycle detection  Central questions: 1. Does iteration converge for a statistical arrival times? 2. Does iteration converge for an approximation of statistical arrival times?

Verification - Iterative  max(A,   )  Inaccuracy less of a problem in general timing analysis, when both operands of the max() function have similar 

Verification – Results  Result: algorithm does converge!  As expected, rate of convergence highly dependent on the target period  Need: more formal proof… Static T=MMC+1 Statististical T=MMC+1 Statististical T=MMC-1 Statististical T=MMC *.8 s s s s s s

Optimization - A Special Case  If w=0 (i.e. the latches are edge- triggered), the departure time is independent of the arrival time  Both the verification and optimization problems become much easier  Can solve a standard optimization problem L AlAl DlDl where T is the clock period  is a clock schedule d is the min path delay D is the max path delay find , maximize

Optimization - Results  Conjunction of inequalities can be approximated using the max function of [Clark 61]  Use conjugate gradient to maximize

Optimization - General  If w≠0, there are cyclic timing dependencies  Idea 1: Cut circuits at points where arrival time is least likely to arrive in transparent window  Idea 2: Optimize “sections” of paths using a method similar to [Zhou 04]

Conclusions  General techniques in statistical timing analysis need work  Verification problem is hard  Optimization problem is harder