Cycling Timing System SDP /10/03 Patrick Bell Emilio Gaudette Eric Johnson Advisor: Ramakrishna Janaswamy

Introduction Project goals: Time the finish of a bike race electronically ● Produce results in real time ● Minimize cost ● Maximize accuracy Race Parameters: ● Finish is determined by the front edge of the front wheel ● Up to 200 bikes ● Finish speeds range from 5 to 60 mph ● Variable width road

Outline ● Current timing technology ● Motivating factors ● Constraints and limitations ● Our design at a glance ● Implementation details ● Project status

Current Technology ● Digital cameras with optical senors are used to create a composite picture of the finish line as each biker crosses. An operator must manually identify each biker and their place from the picture. ● Radio frequency systems are used, but due to terrible accuracy, can only be used to count laps ● A magnetic signal transfer system has an acceptable accuracy but costs $25,000.

Motivating Factors ● Reduce the cost ● affordable to low levels of competitive cycling, such as collegiate races ● target cost under $5000 for an entire system ● Real time results ● provide officials with immediate results ● provide spectators with intermediate lap information ● provide immediate data to coaches and cyclists ● identify racers ● Accuracy ● existing real time systems have an accuracy on the order of seconds ● accurate to at least one millisecond ● consistent and known accuracy for all competitors

● Line of sight cannot be guaranteed in any direction ✗ lasers and RADAR ● Mounted device: must be light-weight and aerodynamic ● cannot interfere with bike operation or performance ● should weigh less than 100 grams ✗ GPS ● Finish speed can reach up to 60 mph ✗ SONAR, current RFID passive tags ● Racer density (finishers/m 2 ) ● high racer density results in data collision ✗ Touch pads, single frequency radio transponders ● Non-standard bike frame dimensions ● In-race equipment changes ● Easily removable ● Variable width road ● Durability Constraints and Limitations

Design: At A Glance ● Wheel diameter is fixed ● determine when the center of the front wheel crosses an imaginary line placed one wheel radius before the actual finish line. ● Place a radio transmitter on the front fork, very close to the center of the front wheel, which transmits a signal at a unique frequency for each bike ● Place receiving antenna system near the finish line (two antennas) imaginary line finish line wheel radius imaginary line finish line

Design: Meeting the Constraints ● Line of sight ✔ radio transmissions do not require line of sight ● Weight and aerodynamics of mounted device ✔ transponders can be designed to be lightweight and compact ● Finish speed can reach up to 60 mph ✔ high frequency transmissions can be read at a high rate of speed ● Racer density (finishers/m 2 ) ✔ unique frequencies ensure no data collisions occur between bikes ● Non-standard bike frame dimensions ✔ front wheel has standard radius

Design: Meeting the Constraints ● In-race equipment changes ✔ transponder is frame mounted, so only rare bike changes need to be accounted for ● Easily removable ✔ transponders can be easily attached / removed ● Variable width road ✔ width of the road is only limited by transponder range ● Durability ✔ transponders can be designed for durability

Implementation: General Setup

Implementation: Math

Implementation: Antenna Setup ● set phase limit to Ф ● shaded area represents locations where phase difference of the signals received at A1 and A2 is ≤ Ф

Implementation: Analog Receiver (AR)

Implementation: Analog Receiver

Implementation: Digital Control Block

Implementation: DCB ● Address Incrementer (AI) ● Iterates from 0 to 255 (counter) ● Corresponds to unique bike ID ● Outputs overflow bit ● Pulser Array (PA) ● Ensure each bike is only counted once ● Controlled by the AI ● MUX ● Selects bike data indicated by AI

Implementation: Digital Control Block

Implementation: DCB – PIC ● Captures lap time data in real time ● Maintains an Address Counter (AC) ● stores the number of AI overflows ● Lap time data is the bike identification (AI) appended to AC ● used to determine bike ID ● used to determine lap time ● Buffers lap time data ● Sends buffered data to PC over serial interface

● PIC runs on interrupts from both the C input and the overflow of the AI ● PIC continually sends out buffered information while not servicing interrupts ● ISR 1 occurs when C goes high ● Buffers lap time data (AC:AI) ● Performs buffer maintenance ● ISR 2 occurs when AI overflows ● Increments AC Implementation: PIC ISRs

Implementation: PC Interface ● Receives lap time data from PIC over serial interface via MAX232 ● Bike ID is lowest order byte (AI) ● Bike time is AC * {AI overflow rate} ● Organize and output timing information ● TV / TV commentators ● Timing board ● Via some other communications media to coaches

Project Status (11 th Major Revision) ● Initial theory analysis ● Phase detection modeled mathematically ● Constraint problems defined and analyzed ● Analog Receiver (AR) ● MATLAB and PSpice simulations complete ● Preliminary hardware design and implementation complete ● Currently under testing ● Digital Control Block (DCB) ● Combinational logic components completed (VHDL) ● PIC buffer and ISR algorithms designed

Future Objectives ● Analog Receiver (AR) ● Build and test AR ● Noise analysis ● Timing analysis ● Digital Control Block (DCB) ● PIC coding ● Test DCB ● PC interface ● Transponder ● Field Testing