CSS 372 Oct 2 nd - Lecture 2 Review of CSS 371: Simple Computer Architecture Chapter 3 – Connecting Computer Components with Buses Typical Bus Structure Bus Structures Synchronous, Asynchronous Typical Bus Signals Two level, Tri-state, Wired Or

Simple Computer Data Paths

Simple Memory Mapped I/O Simple Memory Layout: x0000 – x00FF Trap vectors (Supports Software Interrupts) x0020 [x0400] GETC (Read Char from Keyboard) x0021 [x0430] OUT (Write Character to Console) x0022 [x0450] PUTS (Write string to Console) x0023 [x04A0] IN (Prompt, input character from Keyboard, echo character to Console) x0024 [x04E0] PUTSP (Write “packed” string to Console) x0025 [xFD70] HALT (Turn off run latch in MCR) x0100 – x01FF Interrupt Vectors (Supports Hardware Interrupts) x0200 – x2FFF System Programs & Data (“Operating System”) x3000 – xFDFF User Programs Area xFE00 – xFFFF I/O Programming “Registers” (Mapped I/O Registers) xFE00 KBSR [15 {Ready}, 14 {Intr enable}] (Keyboard Status Register) xFE02 KBDR [7:0{ascii data}] (Keyboard Data Register) xFE04 DSR [15{Done}, 14{Intr enable}] (Display Status Register) xFE06 DDR [7:0{ascii data}] (Display Data Register xFFFE MCR [15{Run latch}] (Machine Control Register)

Simple Interrupts 1)Programmer Action: Enable Interrupts by setting “intr enable” bit in Device Status Reg 2)Enabling Mechanism for device: When device wants service, and its enable bit is set (The I/O device has the right to request service), and its priority is higher than the priority of the presently running program, and execution of an instruction is complete, then The processor initiates the interrupt 4)Process to service the interrupt: The Processor saves the “state” of the program (has to be able to return) The Processor goes into Privileged Mode (PSR bit 15 cleared) Priority level is set (established by the interrupting device) The (USP), (R6)  USP.saved register (UserStackPointer.saved) The (SSP.saved)  R6 (SupervisorStackPointer) The (PC) and the (PSR) are PUSHED onto the Supervisor Stack The contents of the other registers are not saved. Why? The CC’s are cleared 5)The Processor Loads the PC from the Interrupt vector (vectors in 0100:01FF) 6)Interrupt Service Routine is executed Ends with an RTI 7)The stored user PSR (POP into PSR), PC (POP into PC), (R6)  SSP.saved, (USP.saved  R6), and the next instruction fetched

Allocating Space for Variables Global data section –All global variables stored here (actually all static variables) –R4 points to beginning Run-time stack –Used for local variables –R6 points to top of stack –R5 points to top “frame” on stack –New frame for each block (goes away when block exited) instructions global data run-time stack 0x0000 0xFFFF PC R4 R6 R5

Simple Register Convention R0 : Trap routine pass values R1 – R3 : General purpose R4 : Global variable stack pointer R5 : Frame pointer (or Activation Record pointer) R6 : Stack pointer R7 : Return PC value

Simple Activation Record Format Function stacked stuff …….. Local Variables Caller’s Frame Pointer (R5) Caller’s Return PC (R7) Function Return Value Function Pass Value n …….. Function Pass Value 1 R6 R5 X0000 XFFFF

Simple Function Call Implementation 1.Caller pushes arguments (last to first). 2.Caller invokes subroutine (JSR). 3.Callee allocates space for return value, pushes R7 and R5. 4.Callee allocates space for local variables. 5.Callee executes function code. 6.Callee stores result into return value slot. 7.Callee pops local vars, pops R5, pops R7. 8.Callee returns (RET or JMP R7). 9.Caller loads return value and pops arguments. 10.Caller resumes computation…

Chapter 3 Connecting Computer Components with Buses Typical Bus Structure Hierarchical Bus Structures Synchronous, Asynchronous Typical Bus Signals Two level, Tri-state, Wired Or PCI Bus Example

What is a Bus? A communication pathway connecting two or more devices (Computers, Components, I/O, …) Usually broadcast Often grouped –A number of channels in one bus –e.g. 32 bit data bus is 32 separate single bit channels Power lines may not be shown

What do Buses look like? –Parallel lines on circuit boards –Ribbon cables –Strip connectors on mother boards –Sets of wires

Communication with Memory

Communication with I/O

CPU Communication

Data Bus (Subset of Bus) Carries data –Remember that there is no difference between “data” and “instruction” at this level Width is a key determinant of performance –8, 16, 32, 64 bit

Address Bus (Subset of Bus) Identify the source or destination of data e.g. CPU needs to read an instruction (data) from a given location in memory Bus width determines maximum memory capacity of system –e.g has 16 bit address bus giving 64k address space

Control Bus (Subset of Bus) Control and timing information –Memory read/write signal(s) –Interrupt request/acknowledge signal(s) –Clock signal(s) –Etc.

Power/Ground (Subset of bus ?) Provides Power and Reference Levels for Devices May be several voltage levels Ground may be dispersed between signals

Bus Interconnection Scheme

Physical Realization of Bus Architecture

Types of Buses Synchronous Asynchronous (Hand Shaking) Serial (Twisted pair, Coaxial Cable,..) Parallel (Ribbon Cable,

Types of Buses Dedicated –Separate data & address lines Multiplexed –Shared lines –Address valid or data valid control line –Advantage - fewer lines –Disadvantages More complex control Ultimate performance

Physical Considerations for Buses Media (voltage, light) Signal levels Noise Absorption Noise Generation Length Delay (Bandwidth) Power Terminations - Transmission Characteristics