Visualisation and Resolution of Coding Conflicts in Asynchronous Circuit Design A. Madalinski, V. Khomenko, A. Bystrov and A. Yakovlev University of Newcastle upon Tyne

2 Outline Motivation Background Signal Transition Graph and its unfolding State encoding problem Detection of coding conflicts Visualisation and Resolution of conflicts Case study Conclusions and future work

3 Motivation International Technology Roadmap for Semiconductors (ITRS) system complexity  communication over computation communications-centric design  distributed implementation over centralised implementation time domain 1 time domain 2 asynchronous interface (glue-logic)

4 Motivation Design Flow Reachability analysis State encoding Boolean minimization Logic decomposition Technology mapping Specification Signal Transition Graph State Graph Complete State Encoding Next-state functions Decomposed functions Gate netlist Complete State Encoding Next-state functions Decomposed functions Gate netlist Specification Signal Transition Graph dtack- dsr+ lds+ d- lds-ldtack- ldtack+ d+ dtack+ dsr- State Graph dtack-dsr+ dtack-dsr+ dtack-dsr ldtack lds lds+ ldtack+ d+ dtack+dsr- d Complete State Encoding dtack-dsr+ dtack-dsr+ dtack-dsr ldtack lds lds+ ldtack+ d+ dtack+dsr- d csc+ csc Next-state functions Decomposed functions Gate netlist DTACK D DSr LDS LDTACK csc map Resolution of coding conflicts

5 Motivation state coding is a necessary for implementability manual vs. automatic resolution of coding conflicts automatic  can produce sub-optimal solutions manual  crucial for finding good (low-latency, compact & elegant) synthesis solutions interactivity is good! visualisation concept: emphasise on essential & compact elements

6 Signal Transition Graph (STG) Device VME Bus Controller lds ldtack d Data Transceiver Bus dsr dsw dtack dsr lds ldtack d dtack dtack- dsr+ lds+ d- lds-ldtack- ldtack+ d+ dtack+ dsr-

7 dtack- dsr+ lds+ d- lds-ldtack- ldtack+ d+ dtack+ dsr- Signal Transition Graph (STG) Device VME Bus Controller lds ldtack d Data Transceiver Bus dsr dsw dtack Read cycle

8 Implementation problem: State Enoding pairs of semantically different states with the same binary encoding not distinguishable at the circuit level necessary condition for deriving the logic implementation: Complete State Coding (CSC): 2 states may have the same code iff the set of non-input signals is the same

9 dtack-dsr+ dtack-dsr+ dtack-dsr ldtack lds lds+ ldtack+ d+ dtack+dsr- d M’’M’ dtack-dsr+ dtack-dsr+ dtack-dsr ldtack lds lds+ ldtack+ d+ dtack+dsr- d Example: CSC conflict

10 M’’M’ Example: enforcing CSC dtack-dsr+ dtack-dsr+ dtack-dsr ldtack lds lds+ ldtack+ d+ dtack+dsr- d csc+ csc

11 STG unfolding partial order model acyclic net, infinite, simple structure finite complete prefix finite initial part of unfolding alleviate state space explosion problem contains all reachable states more visual then state graphs proven efficient for model checking

12 State Graphs vs. Unfoldings lds- e1e1 e2e2 e3e3 e4e4 e5e5 e6e6 e7e7 e9e9 e 11 e 12 e 10 e8e8 dsr+ ldtack+ dsr- ldtack- lds+ d+ dtack+ d- dtack- dsr+ lds+ M’ M’’ M’ M’’ dtack-dsr+ dtack-dsr+ dtack- dsr ldtack lds lds+ ldtack+ d+ dtack+ dsr- d initial state transitions

13 Visualisation of coding conflicts representation of conflicts as pairs of configurations is not efficient already a small number of conflicts is difficult to depict Propagation effect 888 CSC conflicts!

14 Visualisation of coding conflicts visualising only the essential parts involved in conflicts compact representation avoids explicit representation based on complementary sets {b0+,b1+,b0-,b1-}

15 Coding conflict detection in a prefix integer programming technique V. Khomenko, M. Koutny and A. Yakovlev: Detecting State Coding Conflicts in STGs Using Integer Programming. Proc of DATE’02, IEEE Comp. Soc. Press (2002) CSC conflict representation as unordered conflict pair of configurations C1C1 C2C2

16 Classification of conflicts type I: C 1  C 2 type II: C 1 \C 2 ≠  ≠ C 2 \C 1, and there exist e 1  C 1 \C 2 and e 2  C 2 \C 1 such that e 1 # e 2 Conflicts of type I and II C1C1 C2C2 C1C1 C2C2 e1e1 e2e2

17 Cores complementary set CS=C 1  C 2  C 1,C 2  is a conflict pair  is the symmetric set difference CS is of type I/II if  C 1,C 2  is of type I/II CS is a core if it cannot be represented as union of several disjoint complementary sets

18 Resolution of coding conflicts Core t+ t- introduction of additional internal signals destroying cores insert t+ in a core t- must be added outside the core preserving signal consistency inserted transitions cannot trigger an input signal

19 Visualisation of conflicts: Height map Core 1 Core 3 Core 2 cores often overlap high-density areas are good candidates for signal insertion analogy with physical map in geography A1 A2 A3

20 Height map: an example Core mapHeight map csc 1 +

21 Given an STG with conflicts Overview of resolving process Construction of STG’s prefix & computation of cores

22 Overview of resolving process Conflicts exists? No -> process terminated Yes -> Phase 1 & 2 Location is determinate where t+ & t- is inserted

23 Overview of resolving process Transferring inserted signal to STG Process can consists of several cycles, depending on the number of cores

24 Phase 1 Case study: part of async. AD converter controller csc 1 + Phase 1 Core map Height map

25 csc 1 + Phase 2 csc 1 - Height map Core map csc 1 + Case study: part of async. AD converter controller

26 Case study: Handshake decoupling element Core mapPart of the solving process csc 1 + csc 1 - Phase 1Phase 2 csc 1 +

27 Case study: Handshake decoupling element initial STG STG derived by our method

28 Conclusions approach for visualisation and resolution of state coding conflict was designed main ingredients of the approach compact representation of concurrent behaviour compact representation of conflicts compact representation of constrains for resolution unfolding prefix+ cores+ height map

29 Future work improving our tool ConfRes using concurrency reduction in addition to signal insertion for resolving conflicts using timing assumptions full design cycle based on STG unfoldings, not involving state graphs at any stage ACSD 2003