Chapter 6 Arithmetic

Addition Carry in Carry out

s i = c i +1 = Figure 6.1. Logic specification for a stage of binary addition x i y i Carry-in c i Sum s i Carry-out c i+1 x i y i c i x i y i c i x i y i c i x i y i c i x i y i c i = + ++ y i c i x i c i x i y i DNF (disjunctive normal form)

Logic for a Single Stage

FA x n-1 cncn s n-1 y n-1 FA x0x0 c1c1 s0s0 y0y0 x1x1 C n-1 s1s1 y1y1 … c0c0 Least significant bit (LSB) position Most significant bit (MSB) position N-bit ripple carry adder

n-bit adder X kn-1 c kn s kn-1 y kn-1 X0X0 cncn s0s0 y0y0 XnXn C n-1 S 2n-1 ynyn … c0c0 Cascade of k n-bit adders n-bit adder … S (k-1)n SnSn … … S n-1 X 2n-1 y 2n-1 … X n-1 y n-1

Add/Sub control n-bit adder x n1- x 1 x 0 c n s n1- s 1 s 0 c 0 y n1- y 1 y 0 Figure 6.3. Binary addition-subtraction logic network … … … …

FA X n-1 cncn s n-1 y n-1 FA X0X0 c1c1 s0s0 y0y0 X1X1 C n-1 s1s1 y1y1 … c0c0 Least significant bit (LSB) position Most significant bit (MSB) position N-bit ripple carry adder Timing inputs result

Timing Gate delays –Propagation through the circuit over the longest path From x 0 …y 0 at the LSB position To c n, S n-1 at MSB C n-1 available in 2(n-1) “gate delays” S n-1 available 1 delay later C n 1 delay later –Total of 2n gate delays –+ 2 more to set overflow

Logic for a Single Stage 2 “gate delays” 1 “gate delay”

FA X n-1 cncn s n-1 y n-1 FA X0X0 c1c1 s0s0 y0y0 X1X1 C n-1 s1s1 y1y1 … c0c0 Least significant bit (LSB) position Most significant bit (MSB) position N-bit ripple carry adder 2(n -1) gate delays to here 1 more gate delay to here 2n gate delays + 2 more to set “overflow”

Timing 2 n gate delays: n = 8, 32, 64 Need for “fast adder” Carry lookahead

s i = c i +1 = x i y i c i x i y i c i x i y i c i x i y i c i x i y i c i = + ++ y i c i x i c i x i y i c i+1 = x i y i + (x i + y i ) c i c i+1 = G i + P i C i where G i = x i y i and P i = x i + y i (G = “generate”P = “propagate”) c i+1 = G i + P i G i-1 + P i P i-1 c i-1 … cici

c i+1 = G i + P i G i-1 + P i P i-1 G i-2 + … + P i P i-1 …P 1 G 0 + P i P i-1 …P 0 C 0 Then, the expression for any carry is: For a 4-bit adder: c 0 = G 0 + P 0 c 0 c 1 = G 1 + P 1 G 0 + P 1 P 0 c 0 c 2 = G 2 + P 2 G 1 + P 2 P 1 G 0 + P 2 P 1 P 0 c 0 c 3 = G 3 + P 3 G P 3 P 2 G 1 + P 3 P 2 P 1 G 0 + P 3 P 2 P 1 P 0 c 0

Bit-stage cell x i y i c i + + = G i = x i y i P i = x i + y i Same as Unless x i + y i = 1 and then G i = 1 and it doesn’t matter what P i is x i y i +

The “calculation” from the preceding chart 4 bits => “fan-in to last (left-most) gate is 5 -- the limit for practical application 4-bit carry-lookahead adder

Figure bit carry-lookahead adder built from 4-bit adders (Similarly for 32-bit or 64-bit adders) Carry-lookahead logic 4-bit adder s P 3 I G 3 I c 12 P 2 I G 2 I c 8 s 11-8 G 1 I c 4 P 1 I s 7-4 G 0 I c 0 P 0 I s 3-0 c 16 x y x 11-8 y x 7-4 y x 3-0 y. G 0 II P 0

(13) Multiplicand M 1 1 (143) Product P (11) Multiplier Q x (a) Manual multiplication algorithm Multiplication of Positive Numbers Multiply “by hand” or programmatically

Uses lots of gates (transistors), lots of space on a chip (64 x 64, say) Delay--signal propagation from upper right to lower left-- for an n x n array: 6(n-1) gate delays

Control Sequencer n-bit adder Add/Noadd control MUX Multiplier Q m0m0 C Multiplicand M Register A (initially 0) q0q0 a0a0 m n-1 a n-1 q n-1 Sequential circuit binary multiplier (positive numbers) Shift right 0 0

Multiplicand in M, Multiplier in Q, A initially 0, C initially 0 C is the carry from the adder C, A and Q combined will hold the partial product LSB in Q will determine the Add/Noadd to determine if M is to be added to the partial product C, A and Q are shifted right after each add so LSB in Q always hold next multiplier bit (previous LSB is discarded) Control sequencer will shift and add n times

Initial configuration First cycle Second cycle Third cycle Fourth cycle C A Q Add Shift Add Shift Add Shift Add Shift M Product 13 x Partial product

Signed Operands Positive multiplier and a negative multiplicand: – partial product must be sign extended (to the left as far as possible) Maintains the sign of the partial product

Figure 6.8. Sign extension of negative multiplicand ( -13) (-143) (+11) Sign extension is shown in red

Negative multiplier: –Replace both numbers with their two’s complement (doesn’t change the sign of the result) Proceed as before Just add sign extension hardware to what was discussed for positive numbers Signed Operands

Control Sequencer n-bit adder Add/Noadd control MUX Multiplier Q m0m0 C Multiplicand M Register A (initially 0) q0q0 a0a0 m n-1 a n-1 q n-1 Sequential circuit binary multiplier (signed numbers) Shift right 0 0 Maintain a sign-extended partial product (always positive)

Figure 6.9. Normal multiplication scheme

Multiplier requires adding 4 shifted versions of the multiplicand (30) can also be viewed as the difference between two numbers (32 and 2) (32) (2) (30)

Figure 6.9. Booth multiplication scheme 's complement of the multiplicand

Figure Booth recoding of a multiplier

Multiplier Biti i 1 - Version of multiplicand selected by biti M  1+M  1  M  0M  Figure Booth multiplier recoding table.

Figure Booth recoded multipliers Worst-case multiplier Ordinary multiplier Good multiplier

Figure Longhand division examples

Divisor M n-bit adder Control Sequencer Shift left Dividend Q Quotient setting Add/Subtract Circuit for binary division

Division n times: 1) Shift A and Q left 1 2) Subtract M from A, result in A 3) –if sign of A is 1, set q 0 to 0 and add M back to A (restore A –otherwise set q 0 to 1

Floating Point Representation Need for more than just (say) 32-bit integers –Need larger numbers –Need fractions (some very small) Integers –d 31, d 30, …. d 0.The binary point or –. d 31, d 30, …. d 0 The binary point

Neither is satisfactory Need the binary point to “float” Scientific notation x x x 10 Floating Point Representation

An E of 0 means E of 127 means 2 0 E of 255 means IEEE standard (Intel and other processors conform) binary point

Normalization and the “hidden bit” … … … x … x 2 6 the “hidden bit” (always a 1) Unnormalized: Normalized:

Single precision: ~7 decimal digits of “precision” (7 significant digits) in range to (or to ) Double precision:~16 decimal digits in range to (or to )

Special Values E = 0M = 0value is 0 E = 255M = 0value is “infinity” (result of divide by 0) E = 0 M /= 0“denormal numbers” smaller than the smallest “normal number” gradual underflow E = 255M /= 0NaN result of an invalid operation(undefined) e.g., 0/0, sqrt(-1)