An Arithmetic Structure for Test Data Horizontal Compression Marie-Lise FLOTTES, Regis POIRIER, Bruno ROUZEYRE Laboratoire d’Informatique, de Robotique et de Microelectronique de Montpellier, France DATE ‘04 Laboratory of Reliable Computing Department of Electrical Engineering National Tsing Hua University Hsinchu, Taiwan

2 Reference  An Arithmetic Structure for Test Data Horizontal Compression Marie-Lise FLOTTES, Regis POIRIER, Bruno ROUZEYRE DATE ‘04  Test Data Compression Using Dictionaries with Fixed-Length Indices Lei Li and Krishnendu Chakrabarty VTS ‘03  An Efficient Test Vector Compression Scheme Using Selective Huffman Coding Abhijit Jas, Jayabrata Ghosh-Dastidar, Mon-Eng Ng and Nur A. Touba IEEE Transaction on CAD of IC and System, June 2003  Improving compression ratio, area overhead, and test application time for SOC test data compression / decompression P. T. Gonciari, B. Al-Hashimi and N.Nicolici DAT ‘02

3 Outline  Instruction  Lossless Compression algorithm  Compression principle and De-compressor Architecture  Main Issue  Compression Issue  Timing Issue  Experimental Result  Compare & Conclusion

4 Why need compression ?  Higher circuit densities and a large number of embedded cores will lead the increase of test data volume, which in turn leads to an increase in testing time.  Transmitting test patterns and handshaking between cores and ATE will waste a lot testing time.

5 How to reduce testing cost ?  ATE has limited pin counts and testing time is equal to the testing cost.  More patterns transmit to core, more testing time  Reduce testing cost a. Reduce testing time - compaction b. Reduce testing pin counts - compression n m Channel n < m

6 Compression Method  (1) Easy compression → Hard decompression (2) Hard compression → Easy decompression  Compression Method  Lossless  Lossy  Compression can be executed through software, therefore the dominate area overhead is the circuit of decompression.

7 Lossless Compression Algorithm  Run-Length Coding  Frequency-Directed Run-Length (FDR) & Extend FDR  Huffman  Dictionary Based  Main idea of above algorithms  More common data, shorter bits to represent

8 Run-Length Coding  First bit represents the data is ‘1’ or ‘0’.  Next m bits represent the runs of ‘1’ or ‘0’ m= m= Compression Ratio :

9 FDR & EFDR Source : VTS ‘99

10 Example of Huffman Tree Source : VTS ‘99

11 Simplified Huffman Tree Source : vlsitsa ‘01

12 Variable-Length Input Huffman Compression Source :DAT ‘02

13 Example Source : VTS ‘

14 Example(1/2) maximum degree Sub graph Clique

15 Example(2/2) More this clique New Graph

16 Example Result  Obtain 4 cliques ： {5,6,13,16}, {2,8,14}, {3,4,7}, {1,11}  12 words are encoded, and there are else 4 different words un-coded.  So total need transmit (1+2)*12+(1+8)*4=72 bits.  If no compression, we need transmit 8*16=128 bits. Therefore, after compression, reducing about 43.75% bits needed to transmit to core.

17 Parameter Definition  M : # of ATE channel  N : # of scan chains in CUT  F : # of FF in each scan chain  Initial test sequence { V 1, V 2, … }  Numerous difference D i  D i = V i+1 -V i Source : DATE ‘04

18 M-to-N Horizontal De-compressor Source : DATE ‘04  M pins in ATE  N scan chains in CUT  M < N

19 De-compressor Structure Source : DATE ‘04  Overhead  Adder  N bits-M SRA Shifts Reg./Accumulator

20 SRA Operation Mode  Parallel Mode ( Shift =0 )  Parallel data-in from adder  Transfer test pattern to scan chains in CUT  Semi-Parallel Mode ( Shift =1 )  Store test pattern from ATE  SRA likes many scan chains

21 5bits-3 SRA Source : DATE ‘04  Test Time Evaluate  Parallel mode  One clock cycle  Semi-Parallel mode  clock cycle

22 Shift-in Test Pattern  M test pins in ATE  Max difference is 2 M  Compressible pattern & Un-compressible pattern  Compressible pattern shift-in time   Un-compressible pattern shift-in time 

23 Compression Issue   Reduce D max can reduce # of test pins M  Importance : MSB > LSB Source : DATE ‘04

24 Compression Issue with Don’t Care  Don’t care bit (X) can be 1 or 0  More don’t care bits, higher compression ratio Vk0: x 0 Vk1: 0 x x 1 0 Vk2: x x 1 x x Vk3: 1 x 0 x x Vk4: 0 x 1 x Vk0: x Vk1: 1 x 0 x 0 Vk2: x x x 1 x Vk3: x x x 0 1 Vk4: x x Vk0: Vk1: Vk2: Vk3: Vk4: Dk0: Dk1: Dk2: Dk3: bits

25 Timing Issue  Test pattern transmit time   Total :  Larger P comp, smaller test pattern transmit time    Test pattern transmit time is shorter

26 Experimental Results (1) Source : DATE ‘04  ISCAS89 Benchmark

27 Experimental Results (2)  ISCAS89 Benchmark : S9234  Version 1 6 scan chains & Length 42  Version 2 10 scan chains & Length 25  Version 3 10 scan chains & Length 25 6-to-10 compressor

28 Experimental Results (3) Source : DATE ‘04

29 Conclusion  A useful & simple method for reducing test pin  A low overhead  Adder & Nbits-M SRA  No impact the fault coverage  compressible & un-compressible pattern  Problem  Not use the don’t care bit adequately

30 Conclusion (cont.)  Combine the SRA and 1st scan chain … Scan chain SRA … Scan chain SRA

31 Combination  Combine this approach with dictionary based compression Dictionary Based CompressionArithmetic Compression Grouped pattern Compressed Pattern Un-compressed Pattern