S. Mandayam/ CompArch2/ECE Dept./Rowan University Computer Architecture II: Specialized 0909.444.01/02 Fall 2001 John L. Schmalzel Shreekanth Mandayam.

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Presentation transcript:

S. Mandayam/ CompArch2/ECE Dept./Rowan University Computer Architecture II: Specialized /02 Fall 2001 John L. Schmalzel Shreekanth Mandayam ECE Department Rowan University Lecture 1 October 25, 2001

S. Mandayam/ CompArch2/ECE Dept./Rowan UniversityPlan Intel P4 Quick Review: Integer Representation Sign-Magnitude Twos Complement Quick Review: Integer Arithmetic Floating Point Representation IEEE 754 Standard Floating Point Arithmetic IEEE 754 implementation

S. Mandayam/ CompArch2/ECE Dept./Rowan University Intel P4 Pentium® 4 Processor Pentium® III Processor Celeron™ Processor Mobile Processors A guide to help you make smart technology decisions. Digital Audio Players Home Networking PC Cameras PC Toys Wired Peripherals Wireless Peripherals PCs, products and ideas for the home Let us recommend the right PC for you Find out who sells Intel® processor- based PCs Shop Intel(SM) Store PC Buyer's Guide Vendor Fast Find Home Computing Product Selector

S. Mandayam/ CompArch2/ECE Dept./Rowan University ALU Inputs and Outputs

S. Mandayam/ CompArch2/ECE Dept./Rowan University Quick Review: Integer Representation Sign-Magnitude Twos Complement

S. Mandayam/ CompArch2/ECE Dept./Rowan University Twos Complement: Range -2 n-1 to 2 n-1 -1

S. Mandayam/ CompArch2/ECE Dept./Rowan University Geometric Depiction of Twos Complement Integers

S. Mandayam/ CompArch2/ECE Dept./Rowan University Hardware for Addition and Subtraction

S. Mandayam/ CompArch2/ECE Dept./Rowan University Floating Point: Example Sign bit Biased Exponent Significand/Mantissa/Fraction 8 bits 23 bits Sign of Mantissa

S. Mandayam/ CompArch2/ECE Dept./Rowan University Floating Point: Expressible Numbers

S. Mandayam/ CompArch2/ECE Dept./Rowan University IEEE 754 Standard Parameter Single Precision Single Extended Double Precision Double Extended Word width (bits)32>= 4364>= 79 Exponent width (bits)8>= 1111>= 15 Exponent bias127Unspecified1023Unspecified Max exponent127>= >= Min exponent-126<= <= Number range (base 10)10 -38, Unspecified , Unspecified Mantissa width (bits)23>= 3152>= 63 No. of exponents254Unspecified2046Unspecified No. of fractions2 23 Unspecified2 52 Unspecified No. of values1.98 x 2 31 Unspecified1.98 x 2 63 Unspecified

S. Mandayam/ CompArch2/ECE Dept./Rowan University IEEE 754 Numbers and NaNs NumberSign Biased Exponent FractionValue Positive zero0000 Negative zero100-0 Plus infinity0255 (all 1s)0Infinity Minus infinity1255 (all 1s)0-Infinity Quiet NaN0 or 1255 (all 1s)neq 0NaN Signaling NaN0 or 1255 (all 1s)neq 0NaN Positive normalized nonzero00 < e < 255f2 e-127 (1.f) Negative normalized nonzero10 < e < 255f-2 e-127 (1.f) Positive denormalized00f neq 02 e-126 (0.f) Negative denormalized10f neq 0-2 e-126 (0.f)

S. Mandayam/ CompArch2/ECE Dept./Rowan UniversityReferences William Stallings, Computer Organization and Architecture, 5 th Edition, Prentice-Hall, ftp://ftp.prenhall.com/pub/esm/computer_s cience.s-041/stallings/Slides/COA5e- Slides/ftp://ftp.prenhall.com/pub/esm/computer_s cience.s-041/stallings/Slides/COA5e- Slides/ IA-32 Intel Architecture Software Developer’s Manual Volume 1: Basic ArchitectureIA-32 Intel Architecture Software Developer’s Manual Volume 1: Basic Architecture

S. Mandayam/ CompArch2/ECE Dept./Rowan UniversitySummary