CS 61C L14 State (1) A Carle, Summer 2005 © UCB inst.eecs.berkeley.edu/~cs61c/su05 CS61C : Machine Structures Lecture #14: State and FSMs 2005-07-13 Andy.

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Presentation transcript:

CS 61C L14 State (1) A Carle, Summer 2005 © UCB inst.eecs.berkeley.edu/~cs61c/su05 CS61C : Machine Structures Lecture #14: State and FSMs Andy Carle

CS 61C L14 State (2) A Carle, Summer 2005 © UCB Outline Waveforms State Clocks FSMs

CS 61C L14 State (3) A Carle, Summer 2005 © UCB Review (1/3) Use this table and techniques we learned to transform from 1 to another

CS 61C L14 State (4) A Carle, Summer 2005 © UCB (2/3): Circuit & Algebraic Simplification

CS 61C L14 State (5) A Carle, Summer 2005 © UCB (3/3):Laws of Boolean Algebra

CS 61C L14 State (6) A Carle, Summer 2005 © UCB Signals and Waveforms Outputs of CL change over time With what?  Change in inputs Can graph changes with waveforms …

CS 61C L14 State (7) A Carle, Summer 2005 © UCB Signals and Waveforms: Adders

CS 61C L14 State (8) A Carle, Summer 2005 © UCB Signals and Waveforms: Grouping

CS 61C L14 State (9) A Carle, Summer 2005 © UCB Signals and Waveforms: Circuit Delay

CS 61C L14 State (10) A Carle, Summer 2005 © UCB State With CL, output is always a function of CURRENT input With some (variable) propagation delay Clearly, we need a way to introduce state into computation

CS 61C L14 State (11) A Carle, Summer 2005 © UCB Accumulator Example Want: S=0; for i from 0 to n-1 S = S + X i

CS 61C L14 State (12) A Carle, Summer 2005 © UCB First try…Does this work? Nope! Reason #1… What is there to control the next iteration of the ‘ for ’ loop? Reason #2… How do we say: ‘ S=0 ’? Need a way to store partial sums! … Feedback!

CS 61C L14 State (13) A Carle, Summer 2005 © UCB Circuits with STATE (e.g., register) Need a Logic Block that will: 1. store output (partial sum) for a while, 2. until we tell it to update with a new value.

CS 61C L14 State (14) A Carle, Summer 2005 © UCB Register Details…What’s in it anyway? n instances of a “Flip-Flop”, called that because the output flips and flops betw. 0,1 D is “data” Q is “output” Also called “d-q Flip-Flop”,“d-type Flip-Flop”

CS 61C L14 State (15) A Carle, Summer 2005 © UCB What’s the timing of a Flip-flop? (1/2) Edge-triggered D-type flip-flop This one is “positive edge-triggered” “On the rising edge of the clock, the input d is sampled and transferred to the output. At all other times, the input d is ignored.”

CS 61C L14 State (16) A Carle, Summer 2005 © UCB What’s the timing of a Flip-flop? (2/2) Edge-triggered D-type flip-flop This one is “positive edge-triggered” “On the rising edge of the clock, the input d is sampled and transferred to the output. At all other times, the input d is ignored.”

CS 61C L14 State (17) A Carle, Summer 2005 © UCB Bus a bunch of D FFs together … Register of size N: n instances of D Flip-Flop

CS 61C L14 State (18) A Carle, Summer 2005 © UCB Second try…How about this? Rough timing… Yep!

CS 61C L14 State (19) A Carle, Summer 2005 © UCB Accumulator Revisited (proper timing 1/2)

CS 61C L14 State (20) A Carle, Summer 2005 © UCB Accumulator Revisited (proper timing 2/2)

CS 61C L14 State (21) A Carle, Summer 2005 © UCB Pipelining to improve performance (1/2) Timing…

CS 61C L14 State (22) A Carle, Summer 2005 © UCB Pipelining to improve performance (2/2) Timing…

CS 61C L14 State (23) A Carle, Summer 2005 © UCB Peer Instruction 1 Simplify the following Boolean algebra equation: Q = !(A*B) + !(!A * C) Use algebra, individual steps, etc. Don’t just look at it and figure it out, or I’ll have to start using harder examples.

CS 61C L14 State (24) A Carle, Summer 2005 © UCB Administrivia HW 45 due Monday Project 2 will be released soon If you want to get a little bit ahead (in a moderately fun sort of way), start playing with Logisim:

CS 61C L14 State (25) A Carle, Summer 2005 © UCB Clocks Need a regular oscillator: Wire up three inverters in feedback?… Not stable enough 1->0 and 0->1 transitions not symmetric. Solution: Base oscillation on a natural resonance. But of what?

CS 61C L14 State (26) A Carle, Summer 2005 © UCB Clocks Crystals and the Piezoelectric effect: Voltage  deformation  voltage  … Deformations have a resonant freq. -Function of crystal cut

CS 61C L14 State (27) A Carle, Summer 2005 © UCB Clocks Controller puts AC across crystal: At anything but resonant freqs  destructive interference Resonant freq  CONSTRUCTIVE!

CS 61C L14 State (28) A Carle, Summer 2005 © UCB Signals and Waveforms: Clocks

CS 61C L14 State (29) A Carle, Summer 2005 © UCB FSMs With state elements, we can build circuits whose output is a function of inputs and current state. State transitions will occur on clock edges. present state FlipFlop Combinational Logic input output next state

CS 61C L14 State (30) A Carle, Summer 2005 © UCB Finite State Machines Introduction

CS 61C L14 State (31) A Carle, Summer 2005 © UCB Finite State Machine Example: 3 ones… Draw the FSM… PSInputNSOutput

CS 61C L14 State (32) A Carle, Summer 2005 © UCB Hardware Implementation of FSM + =?

CS 61C L14 State (33) A Carle, Summer 2005 © UCB General Model for Synchronous Systems

CS 61C L14 State (34) A Carle, Summer 2005 © UCB Peer Instruction 2 Two bit counter: 4 States: 0, 1, 2, 3 When input c is high, go to next state -(3->0) When input is low, don’t change state On the transition from state 3 to state 0, output a 1. At all other times, output 0.