Slide 1 ITC 2005 Gunnar Carlsson 1, David Bäckström 2, Erik Larsson 2 2) Linköpings Universitet Department of Computer Science Sweden 1) Ericsson Radio.

Slides:



Advertisements
Similar presentations
Network II.5 simulator ..
Advertisements

Nios Multi Processor Ethernet Embedded Platform Final Presentation
System Integration and Performance
1 Operating Systems Input/Output Management. 2 What is the I/O System A collection of devices that different sub- systems of a computer use to communicate.
System Area Network Abhiram Shandilya 12/06/01. Overview Introduction to System Area Networks SAN Design and Examples SAN Applications.
Lecture Objectives: 1)Explain the limitations of flash memory. 2)Define wear leveling. 3)Define the term IO Transaction 4)Define the terms synchronous.
Performance analysis of a Grid-based Instrumentation Device Farm Luca Berruti 1, Franco Davoli 1, Stefano Vignola 1, Sandro Zappatore 1 1 CNIT – University.
INTELLIGENT PLATFORM MANAGEMENT CONTROLLER FOR NUCLEAR FUSION FAST PLANT SYSTEM CONTROLLERS 17th Real Time Conference IPFN, Lisbon, Portugal, May,
1 Chapter 9 Computer Networks. 2 Chapter Topics OSI network layers Network Topology Media access control Addressing and routing Network hardware Network.
© 2007 Pearson Education Inc., Upper Saddle River, NJ. All rights reserved.1 Computer Networks and Internets with Internet Applications, 4e By Douglas.
A New Household Security Robot System Based on Wireless Sensor Network Reporter :Wei-Qin Du.
CSCI 8150 Advanced Computer Architecture Hwang, Chapter 7 Multiprocessors and Multicomputers 7.1 Multiprocessor System Interconnects.
ESA UNCLASSIFIED – For Official Use Deterministic Communication with SpaceWire Martin Suess CCSDS Spring Meeting /03/2015.
 A system consisting of a number of remote terminal units (or RTUs) collecting field data connected back to a master station via a communications system.
INTRODUCTION TO COMPUTER NETWORKS INTRODUCTION Lecture # 1 (
COMPUTER NETWORKS.
Router Architectures An overview of router architectures.
Building an Application Server for Home Network based on Android Platform Yi-hsien Liao Supervised by : Dr. Chao-huang Wei Department of Electrical Engineering.
Computer Architecture Lecture 08 Fasih ur Rehman.
IEEE-1394 Data Link Design Review Sherry Womack Erik Pace ECE 4040 Dr. Martin Brooke.
Identifying SLC 500™ System Components. SLC 500 System Options  The SLC 500 line of processors comprises both fixed and modular processor styles.:
About Samway Electronic SRL Founded in 2005 in Bucharest, Romania Focused on management and monitoring solutions for telecom/industrial computers Active.
The University of New Hampshire InterOperability Laboratory Introduction To PCIe Express © 2011 University of New Hampshire.
Cis303a_chapt06_exam.ppt CIS303A: System Architecture Exam - Chapter 6 Name: __________________ Date: _______________ 1. What connects the CPU with other.
LOGO BUS SYSTEM Members: Bui Thi Diep Nguyen Thi Ngoc Mai Vu Thi Thuy Class: 1c06.
Remote Access Chapter 4. Learning Objectives Understand implications of IEEE 802.1x and how it is used Understand VPN technology and its uses for securing.
CHAPTER 3 TOP LEVEL VIEW OF COMPUTER FUNCTION AND INTERCONNECTION
1-1 Embedded Network Interface (ENI) API Concepts Shared RAM vs. FIFO modes ENI API’s.
Network Protocol Models and Architecture Networks and Protocols Prepared by: TGK First Prepared on: Last Modified on: Quality checked by: Copyright 2009.
Layer Architecture Layer architecture simplifies the network design. It is easy to debug network applications in a layered architecture network. The network.
1 Microprocessor-based Systems Course 9 Design of the input/output interfaces (continue)
2007 Oct 18SYSC2001* - Dept. Systems and Computer Engineering, Carleton University Fall SYSC2001-Ch7.ppt 1 Chapter 7 Input/Output 7.1 External Devices.
DEVICES AND COMMUNICATION BUSES FOR DEVICES NETWORK
(More) Interfacing concepts. Introduction Overview of I/O operations Programmed I/O – Standard I/O – Memory Mapped I/O Device synchronization Readings:
System Architecture Directions for Networked Sensors Jason Hill, Robert Szewczyk, Alec Woo, Seth Hollar, David Culler, Kris Pister Presented by Yang Zhao.
© 2004 Mercury Computer Systems, Inc. FPGAs & Software Components Graham Bardouleau & Jim Kulp Mercury Computer Systems, Inc. High Performance Embedded.
I/O Computer Organization II 1 Interconnecting Components Need interconnections between – CPU, memory, I/O controllers Bus: shared communication channel.
MBG 1 CIS501, Fall 99 Lecture 18: Input/Output (I/O): Buses and Peripherals Michael B. Greenwald Computer Architecture CIS 501 Fall 1999.
EEE440 Computer Architecture
ECE Department: University of Massachusetts, Amherst ECE 354 Lab 4: Remote Control of a Digital Camera.
XFEL The European X-Ray Laser Project X-Ray Free-Electron Laser Communication in ATCA-LLRF System LLRF Review, DESY, December 3rd, 2007 Communication in.
Modes of transfer in computer
Implementation structure The protocol stack was implemented formerly by UniControls, Inc. under the OS9 Real-Time OS. The new implementation for the VxWorks.
Chapter2 Networking Fundamentals
Development of Programmable Architecture for Base-Band Processing S. Leung, A. Postula, Univ. of Queensland, Australia A. Hemani, Royal Institute of Tech.,
©2008 R. Gupta, UCSD COSMOS Summer 2008 Peripheral Interfaces Rajesh K. Gupta Computer Science and Engineering University of California, San Diego.
Chapter 13 – I/O Systems (Pgs ). Devices  Two conflicting properties A. Growing uniformity in interfaces (both h/w and s/w): e.g., USB, TWAIN.
Presenter : Shao-Chieh Hou 2012/8/27 Second ACM/IEEE International Symposium on Networks-on-Chip IEEE computer society.
4 Linking the Components Linking The Components A computer is a system with data and instructions flowing between its components in response to processor.
JPMA PROJECT PRESENTATION (ITU) 1 INTRODUCTION BLUETOOTH CHAT DESIGN JAVA ON MOBILE DEVICE Presenters Benjamin Boateng Abass Omer Venkateshwar Rao Namilakonda.
Multi-objective Topology Synthesis and FPGA Prototyping Framework of Application Specific Network-on-Chip m Akram Ben Ahmed Xinyu LI, Omar Hammami.
Communication Architecture and Network Protocol Layering Networks and Protocols Prepared by: TGK First Prepared on: Last Modified on: Quality checked by:
Internet Protocol Storage Area Networks (IP SAN)
1 May-2014 Automotive Protocols & Standards. 2 CAN (Controller Area Network)  Overview Controller Area Network is a fast serial bus designed to provide.
XFEL The European X-Ray Laser Project X-Ray Free-Electron Laser Dariusz Makowski, Technical University of Łódź LLRF review, DESY, 3 December 2007 The Importance.
Microsoft ® Official Course Module 6 Managing Software Distribution and Deployment by Using Packages and Programs.
Chapter 3 System Buses.  Hardwired systems are inflexible  General purpose hardware can do different tasks, given correct control signals  Instead.
1 Device Controller I/O units typically consist of A mechanical component: the device itself An electronic component: the device controller or adapter.
Univ. of TehranIntroduction to Computer Network1 An Introduction to Computer Networks University of Tehran Dept. of EE and Computer Engineering By: Dr.
MicroTCA & AdvancedTCA Shelf Management Jiping Cao May, 2009 Controls Conference (RT2009) Beijing China.
XFEL The European X-Ray Laser Project X-Ray Free-Electron Laser Dariusz Makowski, Technical University of Łódź LLRF review, DESY, 3 December 2007 The Importance.
XFEL The European X-Ray Laser Project X-Ray Free-Electron Laser Dariusz Makowski, Technical University of Łódź, DMCS ATCA LLRF project review, DESY, 3-4.
Deterministic Communication with SpaceWire
Lecturer, Department of Computer Application
DEPARTMENT OF COMPUTER SCIENCE
CS 286 Computer Organization and Architecture
Introduction to Microprocessors and Microcontrollers
CS 31006: Computer Networks – The Routers
Packet Switch Architectures
Presentation transcript:

Slide 1 ITC 2005 Gunnar Carlsson 1, David Bäckström 2, Erik Larsson 2 2) Linköpings Universitet Department of Computer Science Sweden 1) Ericsson Radio Network Development Sweden Remote Boundary-Scan System Test Control for the ATCA Standard

Slide 2 ITC 2005 Outline Remote Boundary-Scan System Test Control for the ATCA Standard  Introduction  System Environment  Approach  Demonstration Board  Conclusions

Slide 3 ITC 2005 Introduction  Boundary Scan (BScan) not only used for production interconnect test of boards  In multiboard systems the test controller and the target devices may be located on different boards  How to link BScan between controller and target devices?  Natural solution: BScan control and data must be routed through backplane Boundary Scan in Modern Systems

Slide 4 ITC 2005 Introduction Multiboard Systems Shelf Management Board Application specific boards Backplane

Slide 5 ITC 2005 Introduction BScan Multidrop Central Processor Local Processor Local Processor Local Processor System Management Application Boards Control Path Boundary Scan ATEATE Local BScan Master/Slave System BScan Master/Slave

Slide 6 ITC 2005 Introduction Related Work  Several commercial solutions exist how to link BScan in a backplane environment  National Semiconductor: SCAN Bridge  Based upon: [D.Bhavsar, ITC´91]  Addressing boards and modules by using the instruction scan  Texas instruments: Addressable Shadow Port (ASP)  [L.Whetsel, ITC´92]  Added shadow protocol used to access boards and modules

Slide 7 ITC 2005 Introduction Problem Definition  However, some system architectures do not include BScan in the backplane  The emerging ATCA standard is an example, which will be increasingly deployed  The purpose of this project is to find a way to manage remote BScan control in ATCA based systems

Slide 8 ITC 2005 System Environment ATCA Overview  Advanced Telecommunications Computing Architecture (ATCA)  Contain design specifications and requirements in the following areas:  Mechanical and Dimensions  Power Distribution  Thermal Dissipation  Interfacing and Interconnections  System Management

Slide 9 ITC 2005 System Environment  Intelligent Platform Management Interface (IPMI)  Exposing HW management functions to OS and Management SW  Provides interface and communications for:  Monitoring and Logging  Inventory  Recovery Control  Allows implementation of additional management applications within the IPMI framework System Management (IPMI)

Slide 10 ITC 2005 System Environment System Management (IPMI) SM Shelf Management Board BMC Application Board BMC Application Board Management SW/OS SM = Shelf Manager BMC = Baseboard Management Controller Management Bus (IPMB)

Slide 11 ITC 2005 Synch & Clock I/F Update Channel I/F IPMB-0 Buffers Temperature Sensor Payload Interface Point-to-Point E-Keying Enables Hardware Address [7:0] Power Supply Monitoring Payload Power Enable Management Power DC/DC Converter Monitor/ Controller Enable Blue LED Handle Switch FRU LEDs Bussed E-Keying Enables Bussed E-Keying Enables Payload Fabric I/F Base I/F Metallic Test Bus IPMB-0 Hardware Address Dual – 48V Power BMC to scale BMC Controller

Slide 12 ITC 2005 System Environment  Intelligent Platform Management Bus (IPMB)  Based on the two wire serial I 2 C Bus  Data transfers up to: 100 kbit/s  Maximum message size: 32 bytes  All IPMI messaging, including IPMB, uses a request/response protocol  All IPMB requests must be answered with an IPMB response  Requests and Responses are not automatically paired Management Bus (IPMB)

Slide 13 ITC 2005 Approach  Propose a way to transport BScan data and control using the IPMB  Propose means how to manage embedded tests in IPMI  The solution should fit in the ATCA/IPMI context  Build a demonstration board to validate the proposed solution Project Goals

Slide 14 ITC 2005 Approach New Functionality in IPMI IPMB BMC Application Board Components under test Memory Operator/ Test Program SM Shelf Management Board Memory

Slide 15 ITC 2005 Approach  Command set to interface and control the onboard tests:  Test management commands: oLIST, SEND, RECEIVE, DELETE  Test execution commands: oRUN  Test setup commands: oLINK, OPTIONS  Embedded test data format  National Semiconductor EVF is an example  Based on the Serial Vector Format (SVF) Commands and Data Format

Slide 16 ITC 2005 Approach  IPMB designed to carry short control and status messages  Extended the IPMB protocol to enable transport of BScan control and data  Still follows the rules and requirements set by the standard IPMB protocol  The SM unit is the requester (master) and the BMC units are the responders (slaves)  Mechanisms for dividing larger test files into smaller IPMB packages and re- assembling of packages back into test files has been specified and implemented Transport of BScan Control and Data

Slide 17 ITC 2005 Approach Transport of BScan Control and Data  Transport times of a 77 kB EVF file on IPMB DescriptionMax. packet size P o + P d I 2 C Speed S Total transport time T 3 Standard IPMB restrictions32 B100 kbit/s11.7 s Increased max packet size64 B100 kbit/s8.44 s Fast I 2 C mode32 B400 kbit/s2.94 s I 2 C High speed mode32 B3.4 Mbit/s0.35 s I 2 C High speed mode and Increased max packet size 64 B3.4 Mbit/s0.25 s

Slide 18 ITC 2005 Demonstration Board Shelf Manager Board BackplaneApplication Board SM Operator Interface IPMB SM Operator Interface BMC BSC UUT

Slide 19 ITC 2005 Demonstration Board Operators interface SM-unit BScan controller BMC-unit UUT

Slide 20 ITC 2005 Conclusions  Easy to add BScan functionality to the ATCA/IPMI context  IPMB suitable to carry BScan control and status  IPMB less suitable to carry large tests due to the limitations of the standard.  Can be solved using the higher available I 2 C data transfer speeds and larger IPMB packet sizes