Introduction Designing cost-sensitive real-time control systems for safety-critical applications requires a careful analysis of the cost/fault-coverage.

Slides:



Advertisements
Similar presentations
Embedded System, A Brief Introduction
Advertisements

System-level Architectur Modeling for Power Aware Computing Dexin Li.
SAFe Automotive aRchItecture SAFARI. SAFARI_Presentation_Short_v1.ppt 2 / /P. Cuenot/ © Continental AG ARTEMIS/Call2 R&D Project Proposal Project.
A Hierarchical Co-ordination Language for Interacting Real-time Tasks Arkadeb Ghosal, UC Berkeley Thomas A. Henzinger, EPFL Daniel Iercan, "Politehnica"
Software Modeling SWE5441 Lecture 3 Eng. Mohammed Timraz
Verification/Simulati on –GUI for simulation and formal verification –Simulator: Exploration of dynamic behavior Checking.
MotoHawk Training Model-Based Design of Embedded Systems.
Fault Detection in a HW/SW CoDesign Environment Prepared by A. Gaye Soykök.
An Automata-based Approach to Testing Properties in Event Traces H. Hallal, S. Boroday, A. Ulrich, A. Petrenko Sophia Antipolis, France, May 2003.
Abhijit Davare 1, Qi Zhu 1, Marco Di Natale 2, Claudio Pinello 3, Sri Kanajan 2, Alberto Sangiovanni-Vincentelli 1 1 University of California, Berkeley.
Page 1 Building Reliable Component-based Systems Chapter 16 - Component based embedded systems Chapter 16 Component based embedded systems.
1 DRAFTS DRAFTS Distributed Real-time Applications Fault Tolerant Scheduling Claudio Pinello
Integrated Design and Analysis Tools for Software-Based Control Systems Shankar Sastry (PI) Tom Henzinger Edward Lee University of California, Berkeley.
Methodologies for Wireless Sensor Networks Design Alvise Bonivento Alessandro Pinto Prof. Sangiovanni-Vincentelli U.C. Berkeley.
CS599 Software Engineering for Embedded Systems1 Software Engineering for Real-Time: A Roadmap Presentation by: Mandar Samant Raghbir Singh Banwait.
Causality Interface  Declares the dependency that output events have on input events.  D is an ordered set associated with the min ( ) and plus ( ) operators.
Presenter : Shih-Tung Huang Tsung-Cheng Lin Kuan-Fu Kuo 2015/6/15 EICE team Model-Level Debugging of Embedded Real-Time Systems Wolfgang Haberl, Markus.
Scheduling with Optimized Communication for Time-Triggered Embedded Systems Slide 1 Scheduling with Optimized Communication for Time-Triggered Embedded.
Design of Fault Tolerant Data Flow in Ptolemy II Mark McKelvin EE290 N, Fall 2004 Final Project.
Modeling State-Dependent Objects Using Colored Petri Nets
7th Biennial Ptolemy Miniconference Berkeley, CA February 13, 2007 PTIDES: A Programming Model for Time- Synchronized Distributed Real-time Systems Yang.
Software Testing for Safety- Critical Applications Presented by: Ciro Espinosa & Daniel Llauger.
November 18, 2004 Embedded System Design Flow Arkadeb Ghosal Alessandro Pinto Daniele Gasperini Alberto Sangiovanni-Vincentelli
Interface-based Design Donald Chai EE249. Outline Orthogonalization of concerns Formalisms Interface-based Design Example Cheetah Simulator Future Inroads.
Motivation  Synthesis-based methodology for quick design space exploration enabled by automatic synthesis followed by analysis  Automatic synthesis:
Chess Review May 10, 2004 Berkeley, CA Fault Tolerant Design of Distributed Automotive Systems Claudio Pinello Prof. Sangiovanni-Vincentelli,
1 Embedded Computer System Laboratory RTOS Modeling in Electronic System Level Design.
1 Presenter: Ming-Shiun Yang Sah, A., Balakrishnan, M., Panda, P.R. Design, Automation & Test in Europe Conference & Exhibition, DATE ‘09. A Generic.
, A Contract-Based Methodology for Aircraft Electric Power System Design IEEE TRANSACTIONS ON AEROSPACE AND ELECTRONIC SYSTEMS,pp ,ISSN ,9.
REAL-TIME SOFTWARE SYSTEMS DEVELOPMENT Instructor: Dr. Hany H. Ammar Dept. of Computer Science and Electrical Engineering, WVU.
Alec Stanculescu, Fintronic USA Alex Zamfirescu, ASC MAPLD 2004 September 8-10, Design Verification Method for.
CASTNESS‘11 Computer Architectures and Software Tools for Numerical Embedded Scalable Systems Workshop & School: Roma January 17-18th 2011 Frédéric ROUSSEAU.
VTT-STUK assessment method for safety evaluation of safety-critical computer based systems - application in BE-SECBS project.
Voicu Groza, 2008 SITE, HARDWARE/SOFTWARE CODESIGN OF EMBEDDED SYSTEMS 1 Hardware/Software Codesign of Embedded Systems DESIGN METHODOLOGIES Voicu.
High Performance Physical Modeling and Simulation
1. Introduction 1.1 Background 1.2 Real-time applications 1.3 Misconceptions 1.4 Issues in real-time computing 1.5 Structure of a real-time system.
Extreme Makeover for EDA Industry
An efficient active replication scheme that tolerate failures in distributed embedded real-time systems Alain Girault, Hamoudi Kalla and Yves Sorel Pop.
1 of 14 1/15 Synthesis-driven Derivation of Process Graphs from Functional Blocks for Time-Triggered Embedded Systems Master thesis Student: Ghennadii.
Copyright John C. Knight SOFTWARE ENGINEERING FOR DEPENDABLE SYSTEMS John C. Knight Department of Computer Science University of Virginia.
Framework for the Development and Testing of Dependable and Safety-Critical Systems IKTA 065/ Supported by the Information and Communication.
Introduction Complex and large SW. SW crises Expensive HW. Custom SW. Batch execution Structured programming Product SW.
Page 1 Reconfigurable Communications Processor Principal Investigator: Chris Papachristou Task Number: NAG Electrical Engineering & Computer Science.
1 Digitally Controlled Converter with Dynamic Change of Control Law and Power Throughput Carsten Nesgaard Michael A. E. Andersen Nils Nielsen Technical.
FORMAL VERIFICATION OF ADVANCED SYNTHESIS OPTIMIZATIONS Anant Kumar Jain Pradish Mathews Mike Mahar.
Jon Perez, Mikel Azkarate-askasua, Antonio Perez
BE-SECBS FISA 2003 November 13th 2003 page 1 DSR/SAMS/BASP IRSN BE SECBS – IRSN assessment Context application of IRSN methodology to the reference case.
© 2012 xtUML.org Bill Chown – Mentor Graphics Model Driven Engineering.
C. André, J. Boucaron, A. Coadou, J. DeAntoni,
REAL-TIME SOFTWARE SYSTEMS DEVELOPMENT Instructor: Dr. Hany H. Ammar Dept. of Computer Science and Electrical Engineering, WVU.
MILAN: Technical Overview October 2, 2002 Akos Ledeczi MILAN Workshop Institute for Software Integrated.
MAPLD 2005/254C. Papachristou 1 Reconfigurable and Evolvable Hardware Fabric Chris Papachristou, Frank Wolff Robert Ewing Electrical Engineering & Computer.
6. A PPLICATION MAPPING 6.3 HW/SW partitioning 6.4 Mapping to heterogeneous multi-processors 1 6. Application mapping (part 2)
Modeling and Analysis of Printer Data Paths using Synchronous Data Flow Graphs in Octopus Ashwini Moily Under the supervision of Dr. Lou Somers, Prof.
> Power Supervison Desired Output level Source Diesel Valve Sink Diesel Valve > Valve Regulator Sink T = 40 ms Air Valve CBSE Course The SaveComp Component.
Run-time Adaptive on-chip Communication Scheme 林孟諭 Dept. of Electrical Engineering National Cheng Kung University Tainan, Taiwan, R.O.C.
Mixed Criticality Systems: Beyond Transient Faults Abhilash Thekkilakattil, Alan Burns, Radu Dobrin and Sasikumar Punnekkat.
Tolerating Communication and Processor Failures in Distributed Real-Time Systems Hamoudi Kalla, Alain Girault and Yves Sorel Grenoble, November 13, 2003.
Real-Time Systems, Events, Triggers. Real-Time Systems A system that has operational deadlines from event to system response A system whose correctness.
Accelerating the pace of power electronics development Typhoon RTDS Electronic Design Automation (EDA) for eCars and Power Electronics “Living in Interesting.
ASIC Design Methodology
ITEA3 Project: ACOSAR Advanced Co-Simulation Open System Architecture
IP – Based Design Methodology
Supporting Fault-Tolerance in Streaming Grid Applications
Gabor Madl Ph.D. Candidate, UC Irvine Advisor: Nikil Dutt
Composing Time- and Event-driven Distributed Real-time Systems
Mark McKelvin EE249 Embedded System Design December 03, 2002
Transaction Level Modeling: An Overview
MapReduce: Simplified Data Processing on Large Clusters
Anand Bhat*, Soheil Samii†, Raj Rajkumar* *Carnegie Mellon University
Presentation transcript:

Introduction Designing cost-sensitive real-time control systems for safety-critical applications requires a careful analysis of the cost/fault-coverage trade-offs. This further complicates the tasks of deploying the corresponding embedded SW on the execution platform, typically distributed around the plant. We propose a synthesis-based design methodology that relieves designers from specifying how to tolerate execution platform faults and involves them in the definition of the overall fault-tolerance strategy: how to address plant faults (adaptive control algorithms), selection of a cost-effective execution platform. Verification tools analyze the solution to extract timing and to check the fault behavior (replica determinism, coverage, etc.). Finally a run-time library is being developed for the deployment of the resulting distributed system. Fault Tolerant Design of Distributed Automotive Systems Claudio Pinello Prof. Sangiovanni-Vincentelli, UC Motivation Drive-by-Wire applications Architecture faults (channels, ECUs) –hardware redundancy –software replication –redundancy management Plant Faults (plant, sensors, actuators) –estimation and control algorithms Application faults: bugs –can be reduced by disciplined coding –code generation from formal models –simulation –formal verification Fine CTRL Coarse CTRL Sens Act Input Arbiter Best Output Sens Act Design space exploration Verification provides timing + coverage If not satisfactory? –change architecture more/fewer components, vary the mix of performance –change algorithms introduce pipelining, reduce/increase granularity –change fault behavior degrade sooner/later –provide hints to the synthesis tool replicate some actors, mapping constraints, precedence constraints Specification Synthesis System Faults Design flow Actors: have criticality, inputs may have fan- in from redundant sources (replicas) Execution is synchronous and periodic: at each period all tasks are executed (data driven or time triggered), satisfying precedence constraints Inputs and Arbiters have partial firing rules Programming model: Fault-tolerant Dataflow Metropolis library to model FTDF netlists Support for simulation, fault injection and visualization Early assessment of closed loop behavior in degraded modes Proposed design flow enables –greater separation of concerns application, architecture, fault behavior –formal specification and verification of fault tolerant systems –design space exploration C. Pinello, L. P. Carloni, and A. L. Sangiovanni-Vincentelli "Fault-Tolerant Deployment of Embedded Software for Cost-Sensitive Real-Time Feedback-Control Applications," Proc. Conf. Design, Automation and Test in Europe (DATE), February 2004 Conclusions Connectivity: –bipartite graph Arch ECUs (Electronic Control Units) channels Actuator/Sensor location ECU2ECU1ECU0 Sens Act Sens Act Performance: –matrix of actor/ECU execution times –matrix of data/channel transmission times Timing analysis: dynamic (shown) and time-triggered execution Architecture Fault Behavior Failure patterns P i  Arch –subsets of Arch graph that may fail simultaneously (in a same iteration) For each P i specify which functionalities must be guaranteed –typically functionality chosen based on criticality Sample fault behavior: –{}: all actors –{ECU0} or {ECU1} or {ECU2}: only critical actors Parse.exeSynDEx Merge.exe Input ArbiterBest Output FineCTRL CoarseCTRLSens Act Input ArbiterBest Output ECU0 ECU1 ECU2 CH0 CH1 CoarseCTRL Schedule.exe Fine CTRL Coarse CTRL Sens Act Input Arbiter Best Output Sens Act FaultBehavior ECU0 ECU1 ECU2 CH0 CH1 Sens Input Coarse CTRL Coarse CTRL Fine CTRL Arbiter Best Arbiter Best Output Act Timing Verification Mapping ECU2ECU1ECU0 Sens Act Sens Act Case Studies: BMW, GM Vehicle Level Data-Flow Architecture Supervisory Control Brake by wire Power Unit Coordinator Steer By Wire Forces applied on Vehicle Torque req/ack Directional and Stability Signals Driver Interface Vehicle Dynamics Sensor Input Actuator Output Steering Position Vehicle Speed Torque req/ack