MIPS Pipeline Default behaviour and pipeline organization The University of British ColumbiaEECE 476© 2005 Guy Lemieux

2 WMXDI W W W M MX Hazard Detection Unit Control Forwarding Unit Data Memory Instruction Memory Registers ALU PC = IF.Flush WrData Addr RdData

3 MIPS Pipelining Summary 1 Forwarding –Solves RAW dependence problem between most instructions –Always forward into X stage (destination of forwarding arrow) –Physically, forwarding mux takes results from M and W stages Logically, forwarding takes result from X or M stage of previous clock cycle (origin of forwarding arrow) No need to forward from W because MIPS register file does “write before read” Load-Use Penalty: 1 Cycle –“LW” result ready after M stage (after DataMem access) Too late for forwarding into X –Instruction after LW (the “use-instr”) stalls for 1 cycle Detected by HDU when “use-instr” is in D stage After 1 stall cycle, “use-instr” goes to X, “LW” goes to W, LW result forwarded into X

4 MIPS Pipelining Summary 2 Branch/Jump Delay Penalty: 1 Cycle –Execute all branches/jumps in D stage –Branch may depend on result in earlier instruction Unless told otherwise, stall branch in D (no forwarding) until result is written to register file –Instruction after branch Unless told otherwise, assume standard MIPS specification: 1-cycle delay slot Always execute this instruction in the delay slot

5 MIPS Pipelining Summary 3 Branch/Jump Prediction in MIPS –Assume none by default –Only affects which instructions are fetched immediately after the branch/jump –If branch/jump prediction is specified, assume NO DELAY SLOTS Instead, nullify if prediction is wrong