Lecture 26 Epilogue: Or Everything else you Wanted to Know about Compilers (more accurately Everything else I wanted you to Know) Topics Getreg – Error recovery in YACC/Bison Inherited AttributesReadings: April 24, 2006 CSCE 531 Compiler Construction

– 2 – CSCE 531 Spring 2006 Overview Last Time – Lec25 slides 1-18 Questions on Project 5 Code Generation for Basic Blocks Register Allocation Today’s Lecture Getreg Optimizations Peephole optimization Error Recovery Next Time: Exam Thursday April 2:00 in SWGN 2A27 References: Code generation Code generation Error recovery: p 264, p Error recovery: p 264, p Inherited Attributes Inherited Attributes

– 3 – CSCE 531 Spring 2006 GetReg Getreg called for “x := y op z” returns L a good location for the result  If y is in a register that holds no other values, and Y is not live and has no next-use after this statement Then return the register for y for the value of L Update the address and register descriptions  Else return an empty register if there is one.  Else, if x has a next use in the block or op is an operator that requires a register (e.g., array indexing), then find an occupied register R and store the value(s) it contains in memory (mov R, mem)  If x has no next use in the block select the memory location for x as the value for L.

– 4 – CSCE 531 Spring 2006 Example 9.5 and Figure 9.10 Example 9.5 d := (a-b) + (a-c) + (a-c) Yields three address code T1 := a-b T2 := a-c T3 := T1 +T2 T4 := T3 + T2 d := T4 Statements Code Generated Register Descriptor Address Descriptor regs empty T1 := a-b MOV a, R0 SUB b, R0 R0: T1 T1 in R0 T2 := a-c MOV a, R1 SUB b, R1 R0: T1 R1: T2 T1 in R0 T2 in R1 T3:=T1+T2 ADD R1,R0 R0: T3 R1: T2 T3 in R0 T2 in R1 T4:=T3+T2 ADD R1,R0 R0: T4 R1: T2 T4 in R0 T2 in R1 d := T4 … R0: d R1: T2 d in R0 T2 in R1 MOV R0,d R0: d R1: T2 d in R0 and memory

– 5 – CSCE 531 Spring 2006 Generating Code for other Stat.Types Array indexing Array indexing Pointer assignments Pointer assignments Conditional Conditional

– 6 – CSCE 531 Spring 2006 Register Allocation and Assignment

– 7 – CSCE 531 Spring 2006 Register Assignment for Inner Loops

– 8 – CSCE 531 Spring 2006 Register Assignment for Outer Loops

– 9 – CSCE 531 Spring 2006 Register Assignment by Graph Coloring

– 10 – CSCE 531 Spring 2006 Register Assignment in C Register directive – allows the programmer to suggest to the compiler that a variable be put in a register Register directive – allows the programmer to suggest to the compiler that a variable be put in a register

– 11 – CSCE 531 Spring 2006 DAGs – Directed Acyclic Graphs Figure 9.16 – Dag for inner product code

– 12 – CSCE 531 Spring 2006 Peephole Optimization

– 13 – CSCE 531 Spring 2006 Inherited Attributes An attribute that “inherits” a value from its parent or a sibling in the parse tree.

– 14 – CSCE 531 Spring 2006 L attributed Definitions A syntax directed translation id L-attributeds if each inherited attribute of X j, 1 <= j <= n on the right hand side of A  X 1 X 2 … X j … X n depends only on  The attributes of the symbols X 1 X 2 … X j-1 depends to the left of X j-1 in the production and  The inherited attributes of A.

– 15 – CSCE 531 Spring 2006 Declarations and Types Consider D  T {L.inherited := T.type} L T  int{T.type := integer} T  real{T.type := real} L  {L 1.inherited := L.inherited} L 1 ‘,’ id{ addtype(id.place, L.inherited); } L 1 ‘,’ id{ addtype(id.place, L.inherited); } L  id{ addtype(id.place, L.inherited); }

– 16 – CSCE 531 Spring 2006 Bottom-Up Evaluation of Inherited Attributes Section 5.6 If we know where it is on the stack, we can access it.

– 17 – CSCE 531 Spring 2006 Exam Handout