Pentium 4 and IA-32 ISA ELEC 5200/6200 Computer Architecture and Design, Fall 2006 Lectured by Dr. V. Agrawal Lectured by Dr. V. Agrawal Kyungseok Kim Nov. 3, 2006

IA-32 ISA (CISC) The term means Intel Architecture, 32-bit (sometimes called i386) The term means Intel Architecture, 32-bit (sometimes called i386) Instruction Set Architecture of Intel’s most successful microprocessors, called x86-32 Instruction Set Architecture of Intel’s most successful microprocessors, called x bit extension of the original Intel x86 processor architecture, 16-bit 32-bit extension of the original Intel x86 processor architecture, 16-bit 64-bit architecture IA-64, Itanium Architecture 64-bit architecture IA-64, Itanium Architecture IA-32 expanded by AMD in 2003 to support natively 64-bit, AMD64 (AMD K8 family) IA-32 expanded by AMD in 2003 to support natively 64-bit, AMD64 (AMD K8 family) IA-32e (NetBurst family, Intel Pentium4 and Xeon), IA-32e (NetBurst family, Intel Pentium4 and Xeon), later called EM64T later called EM64T AMD64 and EM64T are backwards compatible with 32-bit code without any performance loss AMD64 and EM64T are backwards compatible with 32-bit code without any performance loss 1

Two Memory Management Real Mode Real Mode -8086, 8088 in DOS -Addressing only the first 1MB of memory -Segment address + Offset address -Segment address: The beginning address of any 64KB memory segment The beginning address of any 64KB memory segment -Offset address: Select any location within the 64KB Memory segment Select any location within the 64KB Memory segment 2

Two Memory Management Protected Mode Protected Mode and above in Windows, Linux and others - Allows the access to data and programs located above the first 1MB of memory - Descriptor decides the memory segment’s location, length, and access rights. 3

Registers Very small number of general purpose registers Very small number of general purpose registers (approx. 4 integer plus 8 FP, versus typical RISC) (approx. 4 integer plus 8 FP, versus typical RISC) Small number of registers makes spilling more frequent Small number of registers makes spilling more frequent Advanced compiler techniques increase register pressure. Advanced compiler techniques increase register pressure. Partial specialization of the registers makes effective compiler scheduling difficult. Partial specialization of the registers makes effective compiler scheduling difficult. 4

IA-32 Instructions, since mid-80’s Classic CISC set derived from extended accumulator architecture Classic CISC set derived from extended accumulator architecture Improved orthogonality in the 32-bit extensions (80386) Improved orthogonality in the 32-bit extensions (80386) Added FP capabilities previously on a coprocessor (80486) Added FP capabilities previously on a coprocessor (80486) Added MultiMedia Extensions MMX as SIMD (single- instruction multiple-data) integer instructions (Pentium II) Added MultiMedia Extensions MMX as SIMD (single- instruction multiple-data) integer instructions (Pentium II) Added Streaming SIMD Extension SSE, most notably consisting of SIMD FP instructions (Pentium III) Added Streaming SIMD Extension SSE, most notably consisting of SIMD FP instructions (Pentium III) Added SSE2, essentially extension of MMX+SSE to 128 bits (Pentium 4) Added SSE2, essentially extension of MMX+SSE to 128 bits (Pentium 4) 5

Instruction Encoding One instr. Coded on 1 to 17 bytes in original IA-32 One instr. Coded on 1 to 17 bytes in original IA-32 Several types of modifiers/ prefixes Several types of modifiers/ prefixes Two combinations of constants of variable length Two combinations of constants of variable length - Immediate and Displacement - Immediate and Displacement -8, 16, and 32-bit -8, 16, and 32-bit 6

Intel Processors 7

Pentium 4 Seventh-Generation x86 architecture by Intel (NetBurst) Seventh-Generation x86 architecture by Intel (NetBurst) Very deep instruction pipeline with the intention of scaling to very high frequencies Very deep instruction pipeline with the intention of scaling to very high frequencies The SSE2 instruction set for faster SIMD integer, and 64bit floating point The SSE2 instruction set for faster SIMD integer, and 64bit floating point Later Pentium 4 models introduced new technological advances such as Hyper-Threading, a feature to make one physical CPU appear as two logical and virtual CPUs. Later Pentium 4 models introduced new technological advances such as Hyper-Threading, a feature to make one physical CPU appear as two logical and virtual CPUs. 8

NetBurst Architecture 9

Conclusion IA-32 is the oldest important ISA around IA-32 is the oldest important ISA around It is not absolutely fixed but constantly evolving with many new add-on It is not absolutely fixed but constantly evolving with many new add-on (MMX, SSE, SSE2, etc.) (MMX, SSE, SSE2, etc.) Intel has managed to continue pushing the performance by adapting to its CICS nature the techniques developed to speed- up newer RISC Processors Intel has managed to continue pushing the performance by adapting to its CICS nature the techniques developed to speed- up newer RISC Processors IA-32 is evolving toward 64 bits IA-32 is evolving toward 64 bits

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