Electrical and Timing Characteristics of Standard Logic Gates (Lecture #2) ECE 331 – Digital System Design

Spring 2011ECE Digital Systems Design2 Standard Logic Gates DeviceLogic Gate 74xx08 Quad 2-input AND gate 74xx32 Quad 2-input OR gate 74xx04 Hex Inverter (NOT gate) 74xx00 Quad 2-input NAND gate 74xx02 Quad 2-input NOR gate 74xx86 Quad 2-input XOR gate Note: “xx” refers to the logic family

Spring 2011ECE Digital Systems Design3 Logic Families TransistorLogic Familyxx Low PowerL High SpeedH SchottkyS Low Power SchottkyLS Advanced SchottkyAS Adv Low Power SchottkyALS FastF High SpeedHC AdvancedAC CMOS TTL

Spring 2011ECE Digital Systems Design4 Comparison of Logic Families

Spring 2011ECE Digital Systems Design5 Example: 74LS08 (see data sheet for 74LS08)

Spring 2011ECE Digital Systems Design6 Example: 74HC08 (see data sheet for 74HC08)

Spring 2011ECE Digital Systems Design7 Basic Electrical Characteristics

Spring 2011ECE Digital Systems Design8 Logic Gates Logic gates are the basic building blocks for (combinational and sequential) logic circuits. They are, however, abstractions.

Spring 2011ECE Digital Systems Design9 Logic Gates In fact, logic gates are electrical circuits.

Spring 2011ECE Digital Systems Design10 Logic Gates As such, the logic levels must be represented using an electrical characteristic. Most technologies use voltages to represent the logic levels.  TTL  CMOS Some, but very few, technologies use currents to represent the logic levels.

Spring Representing Logic Levels Ideally, a single voltage value is specified for each logic level.  VDD (power) → Logic 1  GND (ground) → Logic 0 Logic 1 = high voltage Logic 0 = low voltage

Spring 2011ECE Digital Systems Design12 Representing Logic Levels In reality, a range of voltages is specified for each logic level. GND VDD V 1,MIN V 0,MAX Logic 1 Logic 0 Undefined Threshold voltages

Spring 2011ECE Digital Systems Design13 Representing Logic Levels Furthermore, voltage ranges, for logic 1 and logic 0, are specified for both the input and the output of a logic gate. They are defined in terms of four parameters  V OH = output high voltageV IH = input high voltage  V OL = output low voltageV IL = input low voltage These are specified in the data sheet for the corresponding logic gate. They differ from one logic family to another.

Spring 2011ECE Digital Systems Design14 Representing Logic Levels InputOutput GND VDD V IH V IL Logic 1 Logic 0 Undefined GND VDD V OH V OL Logic 1 Logic 0 Undefined V IH = min. volt. for Logic 1 V IL = max. volt. for Logic 0 V OH = min. volt. for Logic 1 V OL = max. volt. for Logic 0

Spring 2011ECE Digital Systems Design15 Example: 74LS08 V IH, V IL V OH, V OL

Spring 2011ECE Digital Systems Design16 Example: 74LS32 V IH, V IL V OH, V OL

Spring 2011ECE Digital Systems Design17 Example: 74HC32 V IH, V IL V OH, V OL

Spring 2011ECE Digital Systems Design18 Example: 74LS04 V IH, V IL V OH, V OL

Spring 2011ECE Digital Systems Design19 Basic Timing Characteristics

Spring 2011ECE Digital Systems Design20 Time Delay (aka. Latency) A standard logic gate does not respond to a change on one of its inputs instantaneously. There is, instead, a finite delay between a change on the input and a change on the output. The propagation delay of a standard logic gate is defined for two cases:  t PLH = delay for output to change from low to high  t PHL = delay for output to change from high to low

Spring 2011ECE Digital Systems Design21 Time Delay high-to-low transition low-to-high transition t PHL t PLH

Spring 2011ECE Digital Systems Design22 Time Delay The time delay (both t PLH and t PLH ) for a logic gate is specified in its data sheet. The time delay is also known as the  gate delay  propagation delay of the logic gate  latency

Spring 2011ECE Digital Systems Design23 Example: 74LS08 t PHL, t PLH

Spring 2011ECE Digital Systems Design24 Example: 74LS32 t PHL, t PLH

Spring 2011ECE Digital Systems Design25 Example: 74HC32 t PHL, t PLH

Spring 2011ECE Digital Systems Design26 Example: 74LS04 t PHL, t PLH

Spring 2011ECE Digital Systems Design27 Time Delay The propagation delay of a logic circuit can be determined using the time delay of the individual logic gates. The critical path in the logic circuit must be identified.  The critical path is the path with the greatest delay. The propagation delay of a logic circuit can be used to define  When the output of the logic circuit is valid.  The maximum speed of a combinational logic circuit.  The maximum frequency of a sequential logic circuit.

Spring 2011ECE Digital Systems Design28 Questions?