Megapolis Technical Layout The TRACC TSM Group: Vadim Sokolov Joshua Auld Michael Hope.

Slides:



Advertisements
Similar presentations
Starfish: A Self-tuning System for Big Data Analytics.
Advertisements

INTRODUCTION TO SIMULATION WITH OMNET++ José Daniel García Sánchez ARCOS Group – University Carlos III of Madrid.
Describing Complex Products as Configurations using APL Arrays.
Hardware/ Software Partitioning 2011 年 12 月 09 日 Peter Marwedel TU Dortmund, Informatik 12 Germany Graphics: © Alexandra Nolte, Gesine Marwedel, 2003 These.
Resource Management §A resource can be a logical, such as a shared file, or physical, such as a CPU (a node of the distributed system). One of the functions.
MCTS GUIDE TO MICROSOFT WINDOWS 7 Chapter 10 Performance Tuning.
Spark: Cluster Computing with Working Sets
Silberschatz, Galvin and Gagne  2002 Modified for CSCI 399, Royden, Operating System Concepts Operating Systems Lecture 19 Scheduling IV.
Chap 5 Process Scheduling. Basic Concepts Maximum CPU utilization obtained with multiprogramming CPU–I/O Burst Cycle – Process execution consists of a.
MotoHawk Training Model-Based Design of Embedded Systems.
TRANSIMS Research and Deployment Project TRACC TSM Staff Dr. Vadim Sokolov Dr. Joshua Auld Dr. Kuilin Zhang Mr. Michael Hope.
Input/Output Management and Disk Scheduling
Lecture 1: History of Operating System
DISTRIBUTED CONSISTENCY MANAGEMENT IN A SINGLE ADDRESS SPACE DISTRIBUTED OPERATING SYSTEM Sombrero.
INTRODUCTION OS/2 was initially designed to extend the capabilities of DOS by IBM and Microsoft Corporations. To create a single industry-standard operating.
Cs238 CPU Scheduling Dr. Alan R. Davis. CPU Scheduling The objective of multiprogramming is to have some process running at all times, to maximize CPU.
Chapter 13 Embedded Systems
5: CPU-Scheduling1 Jerry Breecher OPERATING SYSTEMS SCHEDULING.
WSN Simulation Template for OMNeT++
The new The new MONARC Simulation Framework Iosif Legrand  California Institute of Technology.
Introduction What is this ? What is this ? This project is a part of a scientific research in machine learning, whose objective is to develop a system,
D Nagesh Kumar, IIScOptimization Methods: M1L4 1 Introduction and Basic Concepts Classical and Advanced Techniques for Optimization.
From Essentials of Computer Architecture by Douglas E. Comer. ISBN © 2005 Pearson Education, Inc. All rights reserved. 7.2 A Central Processor.
Operating Systems Concepts 1. A Computer Model An operating system has to deal with the fact that a computer is made up of a CPU, random access memory.
Overview SAP Basis Functions. SAP Technical Overview Learning Objectives What the Basis system is How does SAP handle a transaction request Differentiating.
EstiNet Network Simulator & Emulator 2014/06/ 尉遲仲涵.
Applied Transportation Analysis ITS Application SCATS.
Self-Organizing Agents for Grid Load Balancing Junwei Cao Fifth IEEE/ACM International Workshop on Grid Computing (GRID'04)
These courseware materials are to be used in conjunction with Software Engineering: A Practitioner’s Approach, 6/e and are provided with permission by.
MCTS Guide to Microsoft Windows 7
Object-Oriented Software Engineering Practical Software Development using UML and Java Chapter 8: Modelling Interactions and Behaviour.
Chapter 6: CPU Scheduling
Copyright © 2006 by The McGraw-Hill Companies, Inc. All rights reserved. McGraw-Hill Technology Education Lecture 5 Operating Systems.
OPERATING SYSTEMS CPU SCHEDULING.  Introduction to CPU scheduling Introduction to CPU scheduling  Dispatcher Dispatcher  Terms used in CPU scheduling.
Multithreading Allows application to split itself into multiple “threads” of execution (“threads of execution”). OS support for creating threads, terminating.
An Integration Framework for Sensor Networks and Data Stream Management Systems.
TRANSIMS Research and Deployment Support. Kick-off meeting. Computational Engineer Transportation Research and Analysis Computing Center Energy Systems.
A Survey of Distributed Task Schedulers Kei Takahashi (M1)
Issues Autonomic operation (fault tolerance) Minimize interference to applications Hardware support for new operating systems Resource management (global.
NIH Resource for Biomolecular Modeling and Bioinformatics Beckman Institute, UIUC NAMD Development Goals L.V. (Sanjay) Kale Professor.
Framework for MDO Studies Amitay Isaacs Center for Aerospace System Design and Engineering IIT Bombay.
1 Threads, SMP, and Microkernels Chapter Multithreading Operating system supports multiple threads of execution within a single process MS-DOS.
Chapter 3 System Performance and Models Introduction A system is the part of the real world under study. Composed of a set of entities interacting.
Introduction to z/OS Basics © 2006 IBM Corporation Chapter 7: Batch processing and the Job Entry Subsystem (JES) Batch processing and JES.
Silberschatz, Galvin and Gagne ©2009 Operating System Concepts – 8 th Edition, Chapter 3: Process-Concept.
OPERATING SYSTEMS CS 3530 Summer 2014 Systems and Models Chapter 03.
Monte-Carlo based Expertise A powerful Tool for System Evaluation & Optimization  Introduction  Features  System Performance.
1 University of Maryland Runtime Program Evolution Jeff Hollingsworth © Copyright 2000, Jeffrey K. Hollingsworth, All Rights Reserved. University of Maryland.
Chapter 1 Basic Concepts of Operating Systems Introduction Software A program is a sequence of instructions that enables the computer to carry.
Motivation: dynamic apps Rocket center applications: –exhibit irregular structure, dynamic behavior, and need adaptive control strategies. Geometries are.
From the customer’s perspective the SRS is: How smart people are going to solve the problem that was stated in the System Spec. A “contract”, more or less.
Module 5: Managing Content. Overview Publishing Content Executing Reports Creating Cached Instances Creating Snapshots and Report History Creating Subscriptions.
Lecture 4 CPU scheduling. Basic Concepts Single Process  one process at a time Maximum CPU utilization obtained with multiprogramming CPU idle :waiting.
Some of the utilities associated with the development of programs. These program development tools allow users to write and construct programs that the.
CPU scheduling.  Single Process  one process at a time  Maximum CPU utilization obtained with multiprogramming  CPU idle :waiting time is wasted 2.
Advance Computer Programming Market for Java ME The Java ME Platform – Java 2 Micro Edition (J2ME) combines a resource- constrained JVM and a set of Java.
Introduction to Machine Learning, its potential usage in network area,
AWS Batch Overview A highly-efficient, dynamically-scaled, batch computing service May 2017.
Chapter 6: CPU Scheduling
Chapter 6: CPU Scheduling
CPU Scheduling G.Anuradha
Chapter 6: CPU Scheduling
Chapter 6: CPU Scheduling
CPU SCHEDULING.
Multithreaded Programming
Presented By: Darlene Banta
Overview of Workflows: Why Use Them?
Chapter 6: CPU Scheduling
Maximizing Speedup through Self-Tuning of Processor Allocation
Chapter 6: CPU Scheduling
Presentation transcript:

Megapolis Technical Layout The TRACC TSM Group: Vadim Sokolov Joshua Auld Michael Hope

Core Megapolis Modules Task Scheduler Data Containers Library Logit Model Subprocessor IO Library Batch Iteration Model for Cluster Operation Car Following Model Lane Choice Model En Route Choice Model Route Choice Model Activity Choice Model Destination Choice Model Mode Choice Model Visual Interface / Model Feedback Mechanism

Task Scheduler Acts as a “job submission” system to the computer Takes requests for work with the following parameters – Function to evaluate – Range of data to evaluate on – Simulation delivery time – Estimated run time – Other functional dependencies (if applicable) Submits “job” to an active thread based on the following parameters – Processor affinity of the thread (cache coherence) – Thread workload – Priority of the job

Data Containers Library Specialized data containers to optimize certain aspects of data use API to data structures rooted in STL API, most will be a wrapper around STL structures Possible factors which will be optimized include: – Minimizing dynamic memory allocation/deallocation – Minimizing memory footprint – Maximizing cache coherence for a given traversal pattern (random access, linear access, periodic access, etc…) – Optimizing proper alignment to cache and page boundaries – Minimizing access time/lookup – Automating parallel operation over the structure Data structures will provide thread coherence when necessary

IO Library Library which handles file structures, reading, writing, and serialization for restart Standardized well-documented formats Three main categories: – Relational database/JSON/XML for interdependent files such as network files – Optimized binary files for extremely fast IO (i.e. snapshot, plan, or serialization) – Simple fixed format human-readable ASCII files which are non-interdependent and non-performance critical Serialization engine will ease restart capabilities for the tool as a whole

Visual Interface Use of TransimsVIS for initial feedback Development of additional module used for interactive feedback during model execution Utilized initially for debugging choice models OpenGL-based May be run in “offline” mode as well

Batch Iteration Model for Cluster Operation Tool to design and execute an iteration scheme Utilizes multiple “experimental design” parameters per iteration – For example, an iteration might spin off 4 separate instances (to run on different nodes) which will test 4 parameter variations – the best result will be used as the input to the next iteration Uses light MPI communication and is targeted at cluster operation, although a single stream iteration scheme on an individual desktop computer would still benefit

Logit Model Subprocesor Highly optimized engine to evaluate many classes of logit models – the basis of agent choice in many transportation models Optimizations would include: – Categorization of problem my logit model type – Factoring calculations by agent type, choice type, and choice target – Minimizing operations for the given logit model type – Utilize assembly-level optimizations to ensure smart register and cache usage Paired with a parser to allow users to define their own logit functions for a given module, i.e. destination choice or actuated signal controller

Interaction of Modules Each module has its’ own specified time resolution for syncing with other modules – Ideally each higher resolution is a multiple of each lower resolution – May eventually be user configurable Operations are assumed to depend only on the state of the system at the beginning of the time resolution, thus run independently without syncing over the course of the operation Higher resolution operations thus don’t expect to receive feedback from these modules until the “sync point” Motivation to have multiple resolutions sync is to understand that the evaluation of a high level choice will waterfall to the low level choices (i.e. choosing a new destination mandates a change of route choice) Some “doctoring” upon sync may be necessary to respond to new conditions which occurred dynamically during the execution window (i.e. new route was chosen but an accident occurred in the link just after the current one, mandating a slight correction in route)

Car Following Model Initially based on the Intelligent Driver Model (Treiber, Hennecke and Helbing) Resolution of module is ~.1 second Storage will consist of locating position, velocity, acceleration, and other persistent choice variables on the link itself to ensure cache coherency Parallelization will be achieved by making an agent’s choice for the next timestep entirely a function of the previous timestep i.e. f(t+1)=g(t+1,f(t))

Discretionary Lane Changing Model Discretionary lane changes initially derived from the MOBIL lane changing model (Kesting, Treiber, and Helbing) The resolution of module is ~1 second Non-discretionary lane changes modeled using gap acceptance and lane change execution models (Choudhury)

Tactical/Strategic Lane Change Model Tactical/Strategic lane change behavior modeled using nested logit discrete choice models (Choudury) – Logit models may be translated into Bayesian network for faster execution of lane change The resolution of module is ~4 seconds Separate implementations available across these situations – Freeway Lane Changing – Freeway Forced Merge – Urban Arterial Intersections – Urban Arterial Mainline Lane choice

En Route Choice Model Utilizes D* or D* Lite to dynamically correct a path which was either damaged or deemed suboptimal en route The resolution of module is ~2 seconds Specialized network data structures used to optimize cache membership when evaluating neighboring nodes

Route Choice Model Multiple Routing Algorithms – Non-time dependent utilizes A*based on prevailing congestion conditions – All to one/one to all implementation of label correcting for batch routing situations – Time dependent label correcting – Time dependent A* (?????) The resolution of module is ~2 seconds Specialized network data structures used to optimize cache membership when evaluating neighboring nodes

Activity Choice/Destination Choice/Mode Choice Model ???????????????????

Project Development Track Task Scheduler Design – API Implementation Data Structures Design – API Implementation Logit Subprocessor Design – API Implementation Choice of default algorithms for each module, functional groups Task Scheduler Implementation Individual module design, split implementation into three phases: – Basic: bare minimum to simply get functionality – Advanced: bare minimum to meet validation requirements – Optimized Advanced: bare minimum to meet performance goals – Flexible: generalization to allow custom modules Data Structures Implementation Individual module “basic” implementation Logit Subprocessor Implementation Implementation of basic IO features / link to TransimsVIS Individual module “advanced” implementation Individual module “advanced optimized” implementations Implementation of mid-level interactive visualizer Feedback necessary restructuring to task scheduler, data structures, subprocessor Implementation of advanced IO features Implementation of iteration library Implementation of “flexible” modules Implementation of “flexible” logit subprocessor Implementation of high-level interactive visualizer