Wafer Preparation Challenge in epitaxial growth : - Achieving defect free films at low temperate. More than half of the yield loss is due to contamination such as organic and metallic impurities surface preparation is important

Wafer Preparation Surface preparation prior to epi growth generally consist of 2 part : (1) ex-situ clean : RCA cleaning (2) in-situ clean : high temperature H2 annealing

RCA and HF dip RCA Clean : (1)Removing the organic and metallic impurities from the silicon surface by oxidizing the silicon surface (2) Forming complexes with the contaminants,which become water-soluble..

RCA Clean 標準步驟 1. GP 4 振 10~15 分鐘 (GP : H 2 O = 1 : 15 ) ( 此步驟通常不做 ) 2. ACE 振 10~15 分鐘, 沖 DI water 5 分鐘 3. H 2 SO 4 : H 2 O 2 = 2 : 1 泡 15~20 分鐘, 沖 DI water 5 分鐘 (H 2 SO 4 can remove organic.) 4.Dip HF 至不沾水, 沖 DI water 5 分鐘

RCA Clean 標準步驟 (SC1) 5. NH 4 OH : H 2 O 2 : H 2 O = 0.05 : 1 : 5 煮 ( 先煮水 ) 15~20 分鐘, 沖 DI water 5 分鐘 (remove particle by forming chemical oxide) (SC2) 6. HCL : H 2 O 2 : H 2 O = 1 : 1 : 6, 煮 15~20 分鐘 ( 先煮水 ), 沖 DI water 5 分鐘 (remove metal ) 7. Dip HF 至不沖水, 沖 DI water 數秒

RCA after with HF last After the RCA clean - the silicon surface is left passivated with a chemical oxide,which protect the surface against recontamination HF dip : Removing the chemical oxide and the native oxide to achieve the atomically clean silicon surface

RCA after with HF last To accomplish low temperature epitaxy, one must have an atomically clean Si surface HF clean 1.The Si surface is Si-H terminated 2.Highly resistant to oxidation 3.May be exposed to room air for several minutes without significant oxidation

After HF Dip HF : DI =1 : 100 H H H H H H H O H H H H passivation

H 2 Prebake If the temp. of H2 bake is higher than 1000°C no HF etch is necessary And surface is better than HF dip followed by a H2 pre-bakes at 900°C or less.

High Temp. Effect of H2 Prebake But high temp. may causes

Low Temp. Bake The commercial UHCVD systems that are capable of bake temperature (EpiGress) usually require 20 minutes at 800 º C to have an O & C free interface. but the problem is : The EpiGress takes a lot time to ramp up to 800 º C then cool to a deposition temperature of º C Not too good for throughput

Low Temp. Bake ASM has developed a novel hydrogen prebake that has the potential lower the bake temperatures (below 700ºC). If this novel technique is combined with plasma NF 3 chamber cleaning at say the benefits to throughput would also be significant

Water Vapor and Bake Conditions Water vapor is the most persistent contaminate in any vacuum system The effectiveness of the bake at a given temperature is directly proportional to the water and oxygen background in a given system

Surface Oxide Formation by Moisture

SiGe Epitaxial growth Choosing a Growth Temperature : - t c (critical thickness) is the most important factor - IF the critical layer thickness for a given Ge fraction is exceeded, misfit dislocation injection occurs.

Critical Thickness

Metastable state

Growth conditions At low Temp. (625 º C) Surface reaction limited Nonthermal equil. Fewer dislocations than expected,when t>t c

Misfit dislocation The thickness of SiGe growth >t c The film relaxs Misfit dislocation This relaxation is catastrophic for SiGe HBT application

Dislocation number The number of dislocation in non-selective area

Dislocation number The number of dislocation in the selective area

Enhancement Factor (EF)

Si 0.8 Ge 0.2 Two samples were studied (A) 150nm with hole edge aligned with {100} direction (B) 200nm with hole edge aligned with {100} direction

Si 0.8 Ge 0.2 {110}{100}

Threading dislocation Threading dislocation in HBT

Threading dislocation

Gradual relaxed buffer

Strain after anneal

Deposition temperature Once this critical thickness guideline is satisfied : Deposition temperature(T) The film quality for the epitaxial film

Film Quality when T decrease, the silane flow must decrease also. ex: T : 700 º C ; 100% silane : 50sccm------will deposit a specular high quality film. but T : 600°C ; 100% silane :50sccm-----the film beome hazy

Film Quality Faceting/Conformality - Lower temperature and the resultant lower growth rates result in less faceting and improved conformality Poly/Si growth ratio for customers who use a field oxide, depending on temp, this ratio can vary. - Low T favors Si(single crystal) growth - High T favors poly growth

Dichlorosilane(DCS) Dcs(SiH 2 Cl 2 )is the only one that has been applied to the growth of SiGe epitaxial layers - SiCl2 on the surface is then thought to react with hydrogen to form HCL and a silicon adatom

Advantage of DCS over silane Specular defect free surface -----Superior surfaces are evident with DCS even when processing at extremely low temperatures as a result of the HCL released in the decomposition. Temperature : DCS : 700C, silane : 600C. Safety -----silane is explosive and highly pyrophoric