MS-SoC Best Practices – Advanced Modeling & Verification Techniques for first-pass success By Neyaz Khan Greg Glennon Dan Romaine

Sponsored By: 2 of 14 Mixed-Signal Verification Challenges Traditional Mixed-Signal Verification Methodology –Well defined & mature on the Digital side – MDV, UVM –Performance & throughput challenges on Analog side Mixed Signal Verification has many Challenges: –Connectivity/Interconnect bug escapes –Digital/Analog interaction bug escapes –Spec vs Functionality Mismatch –Lack of clearly defined Verification Metrics

Sponsored By: 3 of 14 Mixed-Signal Verification Approach Adopt proven digital centric techniques from digital verification –Use Verification Plan to drive Verification effort –Collect Verification Metrics –Constrained Random Stimulus –Automated Checkers using Assertions –Structured test-benches Analog Modeling – Real Number Models –Use Wreals –Used in top-level verification

Sponsored By: 4 of 14 Real Number Modeling for Analog Enable high-speed simulation of analog/mixed-signal blocks by using real (floating-point, continuous) values in discrete time Removes the analog solver dependency from mixed signal verification Can be written by analog designers and/or digital verification engineers RNM languages include –Wreal (part of Verilog-AMS, runs on digital engine) –VHDL –SystemVerilog

Sponsored By: 5 of 14 High Performance Simulation with Real Number Modeling Simulate all possible conversions of 14-bit ADC + 14 bit DAC –Number of conversions = 2**14 = steps –Spice sim takes days; RNM takes seconds “Analog” Real Input “Analog” Real Output Bit 0 Bit 13 V(in) V(out)

Sponsored By: 6 of 14 MS-SoC Verification using Real Number Models Spec s Verification Planning vPlan Analog Design & Verification Real Number Models (wreals) Model Verification Digital wreal Analog Model RF TX/RX FM TX/RX Bluetooth Modem Comm. Processor GPU DSP Application Processor VideoAudio TV LCD Driver USB DDR3MemoryEMIF PMU PLL Plan Driven Advanced Verification Env. UVM with System Verilog TB; MS Assertions; Coverage; Random Stimulus; Automated Checkers; Metrics in vPlan Executable Verif Plan RF TX/RX FM TX/RX Bluetooth Modem Comm. Processor GPU DSP Application Processor VideoAudio TV LCD Driver USB DDR3MemoryEMIF PMU PLL

Sponsored By: 7 of 14 Mixed Signal Metric Driven Verification (MS-MDV) A way to address the functional verification gap between analog and digital environments –Unifies testbench, stimulus, and checking across A/D boundaries –Aimed at improving productivity, predictability, and quality –Takes advantage of proven verification methodologies: UVM applied to MS  UVM-MS Track analog functional correctness using metrics –Measure: voltage, current, frequency, gain over time –Assertion checks (expression can include electrical, real, logic) Metrics are stored in the Coverage database Metrics [Digital + Analog] annotated from Spec and Tracked in vPlan

Sponsored By: 8 of 14 Drv Mon Seq Config UVC Virtual Sequencer Scoreboard Reference Model Test Seq RF TX/RX FM TX/RX Bluetooth Modem Comm. Processor GPU DSP Application Processor VideoAudio TV LCD Driver USB DDR3MemoryEMIF PMU PLL Analog UVC Drv Mon Seq Confi g Drv Mon Seq Confi g Drv Mon Seq Confi g Drv Mon Seq Config Drv Mon Seq Confi g Drv Mon Seq Confi g Drv Mon Seq Confi g Drv Mon Seq Config Analog UVC Drv Mon Seq Config UVC Digital wreal Model Legend : MS-SoC Verification Environment: Applying UVM based Verification to MS Designs: UVM-MS

Sponsored By: 9 of 14 Plan Driven Verification: Example – Verification of Analog ADC Features in the spec are highlighted and mapped to planned coverage Issue: The ADC average results not using the correct number of samples. How was this found? –It starts by planning the coverage for this feature –In vPlan

Sponsored By: 10 of 14 Next the coverage is defined in the environment and mapped back to the planned element in the vPlan Plan Driven Verification: Example – Verification of Analog ADC Coverage is created within the test environment. These results are then pulled into ePlanner. Coverage is created within the test environment. These results are then pulled into ePlanner. Within ePlanner this coverage is mapped back to the planned coverage.

Sponsored By: 11 of 14 Plan Driven Verification: Example – Verification of Analog ADC The vPlan now ensures the function was fully tested –But what verifies whether it is correct? The answer is the reference model! Real number voltage values seen on the port pins are stored in a queue

Sponsored By: 12 of 14 Plan Driven Verification: Example – Verification of Analog ADC The reference model checks the number of samples in the queue and calculates the expected ADC average result The reference model will error if the number of samples is too small Voltage samples are retrieved from the queue and used to calculate a rolling average The final average is then checked against the value in the DUT to be within a fixed margin of error (quantization error) The reference model will flag an error if the check fails

Sponsored By: 13 of 14 Take away: This type of failure would be impossible to catch with visual inspection –Impossible to reliably count 64 ADC samples that access the particular port being checked by visual inspection. –Random voltage stimulus provides a second check that is impossible to visually check Successfully apply UVM-MS to verify MS-SoC Design Plan Driven Verification: Example – Verification of Analog ADC

Sponsored By: 14 of 14 Summary Our Verification team at Maxim has successfully applied UVM-MS to verify complex Mixed-Signal SoC Results have been outstanding The methodology is proven and it really works!