Chapter 11 Instruction Sets Addressing Modes and Formats

Team Members Jose Alvarez Daniel Monsalve Marlon Calero Alfredo Guerrero Oskar Pio Andres Manyoma

Addressing Modes An addressing mode is the method by which an instruction references memory Types of addressing modes: Immediate Direct Indirect Register Register Indirect Displacement (Indexed) Stack

Immediate Addressing Simplest form of addressing Actual data is stored in instruction Value of the operand is stored within instruction Data sizes vary by processor and by instruction No memory reference (other than instruction fetch) required to obtain operand Size of number limited to size of address field

Immediate Addressing Diagram Instruction Opcode Operand

Direct Addressing Instruction points to location of stored value, but value itself is out of memory Single memory reference to access data No additional calculations needed to work out effective address Frequently used for global variables in high level language Limited address space

Direct Addressing Diagram Instruction Opcode Address A Memory Operand

Indirect Addressing Memory pointed to by address field contains the address of the operand Large address space 2n where n = word length Multiple memory accesses to find operand Hence slower

Indirect Addressing Diagram Instruction Opcode Address A Memory Pointer to operand Operand

Register Addressing Specified instruction contains required operand Limited number of registers Small address field needed Leads to shorter instructions, but faster fetch cycle No memory access Fast execution Limited address space

Register Addressing Diagram Instruction Opcode Register Address R Registers Operand

Register Indirect Addressing Very similar to indirect addressing Only one main difference between the two Algorithms: Register Indirect: EA = (R) Indirect: EA = (A) Advantages/disadvantages also similar to those of indirect addressing: Advantage: Large address space (2n) Disadvantage: Extra memory reference

Register Indirect Addressing Diagram Instruction Opcode Register Address R Memory Registers Pointer to Operand Operand

Displacement Addressing Very powerful addressing mode Combines capabilities of direct and register indirect addressing ( EA = A + (R) ) Three common uses for displacement addressing Relative addressing Base-register addressing Indexing

Displacement Addressing (continued) Relative addressing Implicitly referred to in PC. If most memory references near to instruction being executed, use of relative addressing saves address bits in instruction Base-register addressing Convenient means of implementing segmentation Indexed addressing Address field references a main memory address; referenced register contains positive displacement from that address

Displacement Addressing Diagram Instruction Opcode Register R Address A Memory Registers Pointer to Operand + Operand

Stack Addressing Linear array of locations Other names: Pushdown list, last-in-first-out queue Stack is a reverse block of locations Has a pointer associated with it Stack locations in memory are register indirect addressed

Stack Addressing Diagram

x86 Addressing Modes (continued) 8 addressing modes available Immediate Register operand Displacement Base Base with displacement Scaled index with displacement Base with index and displacement Base scaled index with displacement Relative

x86 Addressing Mode Calculation

ARM Addressing Modes Arm has a rich set of addressing modes. Typically they are classified with respect to the type of instruction. Load/Store Addressing Data Processing Instruction Addressing Branch Instructions Load/Store Multiple Addressing

ARM Addressing Modes Load/Store Loads and stores Instructions are the only instructions that reference memory, always done indirectly through a base register plus offset. 3 alternatives are : Offset Preindex Postindex

ARM Data Processing Instruction Addressing & Branch Instructions Or mixture of register and immediate addressing Branch Immediate Instruction contains 24 bit value Shifted 2 bits left On word boundary Effective range +/-32MB from PC

ARM Load/Store Multiple Addressing Load/store subset of general-purpose registers 16-bit instruction field specifies list of registers Sequential range of memory addresses Increment after, increment before, decrement after, and decrement before Base register specifies main memory address Incrementing or decrementing starts before or after first memory access

Instruction Formats Layouts of bits in an instruction Includes opcode Includes (implicit or explicit) operand(s) Usually more than one instruction in an instruction set

Instruction Length Affected by and affects: Memory size Memory organization Bus structure CPU complexity CPU speed Tradeoff between powerful instruction repertoire and saving space

Instruction Length (continued) Should be equal to or multiple of memory transfer length Should be multiple of character length (usually 8 bits) Word length of memory is “natural” unit of organization

Allocation of Bits Tradeoff between number of opcodes and power of the addressing capability More opcodes mean more bits in the opcode field In an instruction format, this reduces number of bits available for addressing Interrelated factors that determine the use of addressing bits:

Allocation of Bits (continued) Number of addressing modes: can be implicit, but sometimes one or more mode bits are needed Number of operands: today’s machines provide for two operands, each requiring its own mode indicator Register versus memory: one operand address is implicit and consumes no instruction bits, but causes awkward programming and many instructions (a total of 8 to 32 user-visible registers is desirable)

30 Allocation of Bits Number of register sets: most machines have one set of 32 general-purpose registers to store data and addresses Architectures like Pentium have more specialized sets, that by a functional split the instruction uses fewer bits Address range: related to number of address bits, has severe limitations (which is why direct addressing is rarely used) With displacement addressing, the range is opened up to the length of the address register

31 Allocation of Bits Address granularity: a factor for addresses that reference memory rather than registers In a system with 16- or 32-bit words, an address can reference a word or a byte at the designer’s choice Byte addressing is convenient for character manipulation but requires more address bits

PDP-8 Instruction Format

PDP-10 Instruction Format

Variable-Length Instruction Make it difficult to decouple memory fetches Fetch part, then decide whether to fetch more, and maybe miss in cache before instruction is complete Fixed length allows full instruction to be fetched in one access

PDP-11 Designed to provide powerful and flexible instruction set within constraints of 16-bit minicomputer Employs set of eight 16-bit general-purpose registers Two of these registers have additional significance One is used as a stack pointer for special-purpose stack operations The other is used as the program counter, which contains the address of the next instruction

PDP-11 (continued) PDP-11 instructions set and addressing capability are complex This increases both hardware cost and programming complexity The advantage is that more efficient or compact programs can be developed

PDP-11 Instruction Format

VAX Most architectures provide a relatively small number of fixed instruction formats To avoid problems two criteria were used in designing the VAX All instructions should have the “natural” number of operands All operands should have the same generality in specification VAX instruction begins with a 1-byte opcode, which suffices to handle most VAX instructions

VAX Instruction Examples

VAX Instruction Formats The remainder of the instructions consists of up to six operand specifiers Is, at minimum, a 1-byte format in which the leftmost 4 bits are the address mode specifier The only exception to this rule is the literal mode, which is signaled by the pattern 00 in the leftmost 2 bits, leaving space for a 6-bit literal Because of this exception, a total of 12 different addressing modes can be specified

VAX Instruction Formats An example uses an 8-, 16-, or 32-bit displacement. An indexed mode of addressing may be used. In this case, the first byte of the operand specifier consists of the 4- bit addressing mode code of 0100 and a 4-bit index register identifier. The remainder of operand specifier consists of base address specifier, which may be one or more bytes. The VAX instruction set provides for a wide variety of operations and addressing modes. This gives the programmer a very powerful and flexible tool for developing programs.

Questions 1) How many x86 addressing modes were presented? Ans: 9- Imme, Reg operand, Displacement, Base, Base with Displacement, Scaled Index with Displacement, Base with index and Displacement, Base with scaled Index and Displacement, Relative. 2) What are the most common addressing modes? Ans: Immediate, direct, indirect, register, register indirect, displacement, stack 3) How many ARM Addressing modes are there? Load/Store addressing, Data Process Inst Addr, Branch Inst, Load/Store multiple Addr.

Questions 4) How many factors can go into determining the use of determining addressing bits? Ans: # of Addr. Modes, # of Operands, Register vs Mem, # of reg sets, Address Range, Address Granularity 5) What is the fastest Addressing mode? Ans: Immediate Opt code + Operand 6) What is an advantage of using Direct addressing mode? Ans: Simplicity Opt code + lower address space. 7) What addressing mode combines the capabilities of direct & reg indirect addr? Ans: Displacement

Questions 8) Which addressing mode it’s also known as pushdown list addressing mode. Ans: Stack Addressing mode. 9) Which of the addressing modes is the simplest? Ans: immediate addressing mode 10) More opcodes mean more ___ in the opcode field? Ans: Bits

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