Evolution in Architectures and Programming Methodologies of Coarse-grained Reconfigurable Computing By: Zain-ul-Abdin and Bertil Svensson.

Slides:



Advertisements
Similar presentations
Multicast Traffic Monitoring on a Nationwide Backbone Network Tao He New Generation Network (NGN) Lab. Department of Electronic and Engineering Tsinghua.
Advertisements

Interconnection Networks: Flow Control and Microarchitecture.
Issues of HPC software From the experience of TH-1A Lu Yutong NUDT.
Goal: Split Compiler LLVM LLVM – DRESC bytecode staticdeployment time optimized architecture description compiler strategy ML annotations C code ADRES.
Programming in Occam-pi: A Tutorial By: Zain-ul-Abdin
© 2006 Cisco Systems, Inc. All rights reserved. MPLS v2.2—8-1 MPLS TE Overview Introducing the TE Concept.
Bottleneck Elimination from Stream Graphs S. M. Farhad The University of Sydney Joint work with Yousun Ko Bernd Burgstaller Bernhard Scholz.
THE RAW MICROPROCESSOR: A COMPUTATIONAL FABRIC FOR SOFTWARE CIRCUITS AND GENERAL- PURPOSE PROGRAMS Taylor, M.B.; Kim, J.; Miller, J.; Wentzlaff, D.; Ghodrat,
The Microprocessor is no more General Purpose. Design Gap.
Lecture 9: Coarse Grained FPGA Architecture October 6, 2004 ECE 697F Reconfigurable Computing Lecture 9 Coarse Grained FPGA Architecture.
Course-Grained Reconfigurable Devices. 2 Dataflow Machines General Structure:  ALU-computing elements,  Programmable interconnections,  I/O components.
PARALLEL PROCESSING COMPARATIVE STUDY 1. CONTEXT How to finish a work in short time???? Solution To use quicker worker. Inconvenient: The speed of worker.
Summary Background –Why do we need parallel processing? Applications Introduction in algorithms and applications –Methodology to develop efficient parallel.
Claude TADONKI Mines ParisTech – LAL / CNRS / INP 2 P 3 University of Oujda (Morocco) – October 7, 2011 High Performance Computing Challenges and Trends.
University of Michigan Electrical Engineering and Computer Science 1 Polymorphic Pipeline Array: A Flexible Multicore Accelerator with Virtualized Execution.
Seven Minute Madness: Special-Purpose Parallel Architectures Dr. Jason D. Bakos.
SCORE - Stream Computations Organized for Reconfigurable Execution Eylon Caspi, Michael Chu, Randy Huang, Joseph Yeh, Yury Markovskiy Andre DeHon, John.
Multithreading and Dataflow Architectures CPSC 321 Andreas Klappenecker.
1 Evgeny Bolotin – ClubNet Nov 2003 Network on Chip (NoC) Evgeny Bolotin Supervisors: Israel Cidon, Ran Ginosar and Avinoam Kolodny ClubNet - November.
A Streaming Multi-Threaded Model Eylon Caspi,Randy Huang,Yury Markovskiy, Joe Yeh,André DeHon,John Wawrzynek BRASS Research Group University of California,
Network-on-Chip: Communication Synthesis Department of Computer Science Texas A&M University.
University of Michigan Electrical Engineering and Computer Science Amir Hormati, Mehrzad Samadi, Mark Woh, Trevor Mudge, and Scott Mahlke Sponge: Portable.
1 A survey on Reconfigurable Computing for Signal Processing Applications Anne Pratoomtong Spring2002.
Operating Systems Should Manage Accelerators Sankaralingam Panneerselvam Michael M. Swift Computer Sciences Department University of Wisconsin, Madison,
TECHNOLOGY GUIDE THREE Emerging Types of Enterprise Computing.
Conference title1 A New Methodology for Studying Realistic Processors in Computer Science Degrees Crispín Gómez, María E. Gómez y Julio Sahuquillo DISCA.
Lecture 2: Field Programmable Gate Arrays September 13, 2004 ECE 697F Reconfigurable Computing Lecture 2 Field Programmable Gate Arrays.
Paper Review I Coarse Grained Reconfigurable Arrays Presented By: Matthew Mayhew I.D.# ENG*6530 Tues, June, 10,
Coarse and Fine Grain Programmable Overlay Architectures for FPGAs
Software Pipelining for Stream Programs on Resource Constrained Multi-core Architectures IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEM 2012 Authors:
A RISC ARCHITECTURE EXTENDED BY AN EFFICIENT TIGHTLY COUPLED RECONFIGURABLE UNIT Nikolaos Vassiliadis N. Kavvadias, G. Theodoridis, S. Nikolaidis Section.
Uncovering the Multicore Processor Bottlenecks Server Design Summit Shay Gal-On Director of Technology, EEMBC.
Efficient Mapping onto Coarse-Grained Reconfigurable Architectures using Graph Drawing based Algorithm Jonghee Yoon, Aviral Shrivastava *, Minwook Ahn,
S AN D IEGO S UPERCOMPUTER C ENTER N ATIONAL P ARTNERSHIP FOR A DVANCED C OMPUTATIONAL I NFRASTRUCTURE On pearls and perils of hybrid OpenMP/MPI programming.
Course Wrap-Up Miodrag Bolic CEG4136. What was covered Interconnection network topologies and performance Shared-memory architectures Message passing.
Frank Casilio Computer Engineering May 15, 1997 Multithreaded Processors.
Parallel Computing Department Of Computer Engineering Ferdowsi University Hossain Deldari.
CS 8501 Networks-on-Chip (NoCs) Lukasz Szafaryn 15 FEB 10.
Distributed Computing CSC 345 – Operating Systems By - Fure Unukpo 1 Saturday, April 26, 2014.
COARSE GRAINED RECONFIGURABLE ARCHITECTURE FOR VARIABLE BLOCK SIZE MOTION ESTIMATION 03/26/
ISSS 2001, Montréal1 ISSS’01 S.Derrien, S.Rajopadhye, S.Sur-Kolay* IRISA France *ISI calcutta Combined Instruction and Loop Level Parallelism for Regular.
Lecture 13: Logic Emulation October 25, 2004 ECE 697F Reconfigurable Computing Lecture 13 Logic Emulation.
Next Generation Operating Systems Zeljko Susnjar, Cisco CTG June 2015.
Reconfigurable Computing Ender YILMAZ, Hasan Tahsin OĞUZ.
COARSE GRAINED RECONFIGURABLE ARCHITECTURES 04/18/2014 Aditi Sharma Dhiraj Chaudhary Pruthvi Gowda Rachana Raj Sunku DAY
Profile Guided Deployment of Stream Programs on Multicores S. M. Farhad The University of Sydney Joint work with Yousun Ko Bernd Burgstaller Bernhard Scholz.
Computer Architecture SIMD Ola Flygt Växjö University
Survey of multicore architectures Marko Bertogna Scuola Superiore S.Anna, ReTiS Lab, Pisa, Italy.
TECHNOLOGY GUIDE THREE Emerging Types of Enterprise Computing.
Parallel Processing Presented by: Wanki Ho CS147, Section 1.
Mapping of Regular Nested Loop Programs to Coarse-grained Reconfigurable Arrays – Constraints and Methodology Presented by: Luis Ortiz Department of Computer.
Self-Tuned Distributed Multiprocessor System Xiaoyan Bi CSC Operating Systems Dr. Mirela Damian.
Implementing Tile-based Chip Multiprocessors with GALS Clocking Styles Zhiyi Yu, Bevan Baas VLSI Computation Lab, ECE Department University of California,
Classification of parallel computers Limitations of parallel processing.
Lecture 13 Parallel Processing. 2 What is Parallel Computing? Traditionally software has been written for serial computation. Parallel computing is the.
Runtime Reconfigurable Network-on- chips for FPGA-based systems Mugdha Puranik Department of Electrical and Computer Engineering
COMP 740: Computer Architecture and Implementation
Topics Coarse-grained FPGAs. Reconfigurable systems.
Distributed and Parallel Processing
Ottawa, January 9, FETCH FlexTiles: runtime mapping of hardware accelerators on 3D self-adaptive heterogeneous manycore Olivier Sentieys INRIA.
Distributed Processors
A Common Machine Language for Communication-Exposed Architectures
Pablo Abad, Pablo Prieto, Valentin Puente, Jose-Angel Gregorio
Instructor: Dr. Phillip Jones
Israel Cidon, Ran Ginosar and Avinoam Kolodny
Toward a Unified HPC and Big Data Runtime
Routing Without Flow Control Hot-Potato Routing Simulation
Characteristics of Reconfigurable Hardware
Network-on-Chip Programmable Platform in Versal™ ACAP Architecture
Example of Event-Based Video Data (Touch-down Scenario)
Presentation transcript:

Evolution in Architectures and Programming Methodologies of Coarse-grained Reconfigurable Computing By: Zain-ul-Abdin and Bertil Svensson

"Evolution in Arch. and Prog. Methodologies of Coarse-grained RC", Zain-ul-Abdin, Bertil Svensson 2 Outline Motivation Scope Architectural Characteristics Computation Models Coarse-grained Reconfigurable Archietctures Discussion Future Trends

"Evolution in Arch. and Prog. Methodologies of Coarse-grained RC", Zain-ul-Abdin, Bertil Svensson 3 Motivation Emergence of architectures different from Von Neuman’s paradigm of computing Growing focus towards Reconfigurable computing based on data-streaming: –Increased Performance –Run-time Reconfiguration –Power Efficiency Need for Models of Computations –Enhance the understanding of the developer to organize computations –Utilizes the expilicit concurrency in the underlying HW

"Evolution in Arch. and Prog. Methodologies of Coarse-grained RC", Zain-ul-Abdin, Bertil Svensson 4 Scope

"Evolution in Arch. and Prog. Methodologies of Coarse-grained RC", Zain-ul-Abdin, Bertil Svensson 5 Architectural Characteristics Granularity – Fine-grain/Coarse-grain Reconfigurability –Reconfiguration Overheads: Latency, Speed Interconnection Networks –Characteristics: Network topology, Flow control, Routing, QoS Energy Efficiency Scalability

"Evolution in Arch. and Prog. Methodologies of Coarse-grained RC", Zain-ul-Abdin, Bertil Svensson 6 Computation Models Stream Processing Model –Languages: StreamIt, StreamC/KernelC, TDF CSP based Model –Languages: Handel-C, Streams-C, Mobius Spatial Computation Model –Pegasus Kahn Process Networks –Compaan, Ambric structural object programming language

"Evolution in Arch. and Prog. Methodologies of Coarse-grained RC", Zain-ul-Abdin, Bertil Svensson 7 Coarse-grained Reconfigurable Architectures Classification –Hybrid architectures –Array of functional units –Array of processors –Array of soft processors

"Evolution in Arch. and Prog. Methodologies of Coarse-grained RC", Zain-ul-Abdin, Bertil Svensson 8 Coarse-grained Reconfigurable Architectures CategoriesHybrid Architectures Arrays of FUs Array of Processors Example Arch. MorphoSys, Zippy, Tartan, DAPDNA MATRIX, PACT XPP, SiliconHive, Mathstar, NEC DRP RAW, Picochip, Ambric Array of Soft Processors –Mitrionics Virtual Processor

"Evolution in Arch. and Prog. Methodologies of Coarse-grained RC", Zain-ul-Abdin, Bertil Svensson 9 Discussion Summary of features of MoC Features MoC Stream Processing CSPKPNSpatial Comp. Synchronism SynchronousAsynchronous Determinism DeterministicNon- deterministic Deterministic Buffering BoundedNoneUnboundedNone

"Evolution in Arch. and Prog. Methodologies of Coarse-grained RC", Zain-ul-Abdin, Bertil Svensson 10 Discussion Relationship between MoC and CG Arch.

"Evolution in Arch. and Prog. Methodologies of Coarse-grained RC", Zain-ul-Abdin, Bertil Svensson 11 Discussion Trends in Relative complexity of CG Arch.

"Evolution in Arch. and Prog. Methodologies of Coarse-grained RC", Zain-ul-Abdin, Bertil Svensson 12 Future trends Architectural trends (GALS) Computing Model trends (Streaming/CSP/Process Networks) Technology trends (i.e. Nanoscale devices)