1 EE24C Digital Electronics Project Theory: Sequential Logic (part 2)

2 Design example 1: EE19D Exam Q5 A serial binary adder adds two binary numbers X1 and X2 of arbitrary length, producing the numerical sum Z = X 1 + X 2. The input numbers are entered into the adder serially, i.e., bit by bit, and the result is also sent out serially. In one clock cycle corresponding to time t, the adder can receive 2 bits x 1 (t) and x 2 (t) of X 1 and X 2 and compute 1 bit z(t) of Z. Clearly each 1-bit addition can produce a carry signal c(t) which affect the addition to be done in the next clock period. Thus the two possible circuit states can exist: S 0 meaning no carry signal was produced in the preceding clock cycle, i.e., c(t-1) = 0; and S 1, meaning c(t-1) = 1. The addition performed at each step must then take the form x 1 (t) + x 2 (t) + c(t-1), where c(t-1) is determined from the present state at time t.

3 StateInput x 1 x S0S0 S0,0S0,1 S1,1 S1S1 S0,1S1,0 S1,1 State Table

4 State Diagram

5 entity serial_adder is Port ( Clk : in std_logic; X : in std_logic; Y : in std_logic; Z : out std_logic); end serial_adder;

6 architecture Behavioral of serial_adder is type stateM is (S0, S1); signal pstate, nstate: stateM; signal val: std_logic_vector (1 downto 0); begin process(pstate, nstate, X, Y) begin val <= X&Y; case pstate is when S0 => case val is when "00" => nstate <= S0; Z <= ‘0’; when "01" => nstate <= S0; Z <= ‘1’; when "10" => nstate <= S0; Z <=’1’; when "11" => nstate <= S1; Z<= ‘0’; when others => NULL; end case;

7 when S1 => case val is when "00" => nstate <= S0; Z<= ‘1’; when "01" => nstate <= S1; Z<= ‘0’; when "10" => nstate <= S1; Z <= ‘0’; when "11" => nstate <= S1; Z <= ‘1’; when others => NULL; end case; when others => NULL; end case; end process;

8 process begin wait until Clk'event and Clk='1'; pstate <= nstate; end process; end Behavioral;

9 Design Example 2 We want to implement the logic circuit of a sequential serial comparator that determines which of the two serial multi-bit numbers, X and Y, of equal length, is larger. Assume X and Y are unsigned, and the least significant bit is present first. The circuit has three output signals: XEQY (X equal to Y), XLTY (X less than Y), and XGTY (X greater than Y). For example, assume that: The input sequence for X for the first four clock cycles is 0,1,0,0 The input sequence for Y for the first four clock cycles is 0,0,1,0 Then: - The output for XEQY should be 1,0,0,0 - The output for XLTY should be 0,0,1,1 - The output for XGTY should be 0,1,0,0

10 Moore State Machine

11 State/Output Table PSNS: Q1*Q0*Outputs Q1Q0XY=00XY=01XY=10XY=11XEQYXLTYXGTY

12 entity statecomp is Port ( Clk : in std_logic; X : in std_logic; Y : in std_logic; XeqY : out std_logic; XltY : out std_logic; XgtY : out std_logic); end statecomp;

13 architecture Behavioral of statecomp is type stateM is (S0, S1, S2); signal pstate, nstate: stateM; signal val: std_logic_vector (1 downto 0); begin process(pstate, nstate, X, Y) begin val <= X&Y; case pstate is

14 when S0 => XeqY <= '1'; XltY <= '0'; XgtY <= '0'; case val is when "00" => nstate <= S0; when "01" => nstate <= S1; when "10" => nstate <= S0; when "11" => nstate <= S2; when others => NULL; end case;

15 when S1 => XeqY <= '0'; XltY <= '1'; XgtY <= '0'; case val is when "00" => nstate <= S1; when "01" => nstate <= S1; when "10" => nstate <= S2; when "11" => nstate <= S1; when others => NULL; end case;

16 when S2 => XeqY <= '0'; XltY <= '0'; XgtY <= '1'; case val is when "00" => nstate <= S2; when "01" => nstate <= S1; when "10" => nstate <= S2; when "11" => nstate <= S2; when others => NULL; end case; when others => NULL; end case; end process;

17 process begin wait until Clk'event and Clk='1'; pstate <= nstate; end process; end Behavioral