ISSS ’98 University of Rennes I IFSIC / IRISA C.Wolinski Hierarchical Conditional Dependency Graphs for False Path Identification A.Kountouris, C.Wolinski

ISSS ’98 University of Rennes I IFSIC / IRISA C.Wolinski Our New Co-design System Under Construction HCDG Specification : SIGNAL, C, VHDL, Code Generation Transformations : scheduling partitioning optimization Clock Calculation Estimation of: timing size power memory etc. Constraints System Description Parameters C VHDL Assembly for Target Processor Interface generation SimulationSynthesis

ISSS ’98 University of Rennes I IFSIC / IRISA C.Wolinski CCFG Topological Sort High-level specification Hardware C, C, VHDL, Signal Final HCDG Methodology used Scheduling under constraints Hardware Resources Sharing False Path Detection Initial HCDG Parsing Hierarchization process redundant clock removal refining of clock inclusion relations Treatment of arithmetic relations (rel. graphs) : a > 5 b < 5 a < b a 5b Mutual Exclusiveness Detection Process Clock Calculation for each Path in CCFG Conditional Control Flow Graph

ISSS ’98 University of Rennes I IFSIC / IRISA C.Wolinski Hierarchical Conditional Dependency Graph inc ?a !b ?c Nodes correspond to operations that assign values to variables. Clock hierarchy implemented as a hierarchy of BDD trees and represents the inclusion relations between clocks If H2 * H3 = false then H2  H3 and H2  H5 ( H5  H3) end if Mutual Exclusiveness Detection Process Each node is labeled by two clocks : utilization clock definition clock H1 H4 H5 H3 H6 H6=H4+H5 H1 H2 H3 H5 H4H6 Clocks

ISSS ’98 University of Rennes I IFSIC / IRISA C.Wolinski process jian(a, b, c, d, e, f, g, x, y) in port a[8], b[8], c[8], d[8], e[8], f[8], g[8]; in port x, y; out port u[8], v[8]; { static T1; static T2[8], T3[8], T4[8], T5[8]; T1 = (a + 1 b) < c; T2 = d + 2 e; T3 = c + 3 1; if (y) { if (T1) u = T3 + 4 d; /*u1 */ else if (!x) u = T2 + 5 d; /*u2 */ if (!T1 && x) v = T2 + 6 e; } else { T4 = T3 + 7 e; T5 = T4 + 8 f; u = T5 + 9 g; /*u3 */ } JIAN Benchmark Clocks Operations

ISSS ’98 University of Rennes I IFSIC / IRISA C.Wolinski process jian(a, b, c, d, e, f, g, x, y) in port a[8], b[8], c[8], d[8], e[8], f[8], g[8]; in port x, y; out port u[8], v[8]; { static T1; static T2[8], T3[8], T4[8], T5[8]; T1 = (a + 1 b) < c; T2 = d + 2 e; T3 = c + 3 1; if (y) { if (T1) u = T3 + 4 d; /*u1 */ else if (!x)u = T2 + 5 d; /*u2 */ if (!T1 && x)v = T2 + 6 e; } else { T4 = T3 + 7 e; T5 = T4 + 8 f; u = T5 + 9 g; /*u3 */ } } process jian(a, b, c, d, e, f, g, x, y) in port a[8], b[8], c[8], d[8], e[8], f[8], g[8]; in port x, y; out port u[8], v[8]; { static T1; static T2[8], T3[8], T4[8], T5[8]; T1 = (a + 1 b) < c; T2 = d + 2 e; T3 = c + 3 1; if (y) { if (T1) u = T3 + 4 d; /*u1 */ else if (!x)u = T2 + 5 d; /*u2 */ if (!T1 && x)v = T2 + 6 e; } else { T4 = T3 + 7 e; T5 = T4 + 8 f; u = T5 + 9 g; /*u3 */ } } JIAN Benchmark

ISSS ’98 University of Rennes I IFSIC / IRISA C.Wolinski JIAN Benchmark process jian(a, b, c, d, e, f, g, x, y) in port a[8], b[8], c[8], d[8], e[8], f[8], g[8]; in port x, y; out port u[8], v[8]; { static T1; static T2[8], T3[8], T4[8], T5[8]; T1 = (a + 1 b) < c; T2 = d + 2 e; T3 = c + 3 1; if (y) { if (T1) u = T3 + 4 d; /*u1 */ else if (!x)u = T2 + 5 d; /*u2 */ if (!T1 && x)v = T2 + 6 e; } else { T4 = T3 + 7 e; T5 = T4 + 8 f; u = T5 + 9 g; /*u3 */ } } ?a H1 +3 H1 H4 ?b H1 ?d H1 ?e H1 ?c H1 1 ?f H1 +1 H1 H2 +5 H10 +6 H9 +4 H6 ?g H1 +9 H3 !u H5 +8 H3 +7 H3 +2 H1 H7 !v H9 H1 H2H3H4H5 H6H7H8 H9H10

ISSS ’98 University of Rennes I IFSIC / IRISA C.Wolinski JIAN Benchmark Start end H1 H3 H2 H7 H10 H9 H6 H9 H8 H1 N3 N0 N1 N2 N4 N5 N6 C01 C41 C22 C21 C32 C31 C42 C51 C12 C11 CCFG ?a H1 +3 H1 H4 ?b H1 ?d H1 ?e H1 ?c H1 1 ?f H1 +1 H1 H2 +5 H10 +6 H9 +4 H6 ?g H1 +9 H3 !u H5 +8 H3 +7 H3 +2 H1 H7 !v H9 H1 H2H3H4H5 H6H7H8 H9H10

ISSS ’98 University of Rennes I IFSIC / IRISA C.Wolinski {path1=C01,C12;clock=H1*H3 OK}{path1=C01,C12;clock=H1*H3 OK path2= C01,C11,C22,C41;clock=H1*H2*H6*H9 NO path3= C01,C11,C22,C31,C41;clock=H1*H2*H7*H9*H9 OK path4= CO1,C11,C21,C32,C41;clock=H1*H2*H7*H10*H9 NO} {path1=C01,C12;clock=H1*H3 OK path2= C01,C11,C22,C41;clock=H1*H2*H6*H9 NO path3= C01,C11,C22,C31,C41;clock=H1*H2*H7*H9*H9 OK path4= CO1,C11,C21,C32,C41;clock=H1*H2*H7*H10*H9 NO path5= C01,C11,C22,C42;clock=H1*H2*H6*H8 OK path6= C01,C11,C22,C31,C42;clock=H1*H2*H7*H9*H8 OK path7= CO1,C11,C21,C32,C42;clock=H1*H2*H7*H10*H8 OK} Start end H1 H3 H2 H7 H10 H9 H6 H9 H8 H1 N3 N0 N1 N2 N4 N5 N6 C01 C41 C22 C21 C32 C31 C42 C51 C12 C11 CCFG JIAN Benchmark {path1=C01,C11;clock=H1*H2 OK} {path1=C01;clock=H1 OK} {path1=C01,C11,C21;clock=H1*H2*H7 OK} {path1=C01,C11,C22;clock=H1*H2*H6 OK}{path1=C01,C11,C22;clock=H1*H2*H6 OK path2=C01,C11,C22,C31;clock=H1*H2*H7*H9 OK} {path1=C01,C11,C22;clock=H1*H2*H6 OK path2=C01,C11,C22,C31;clock=H1*H2*H7*H9 OK path3=CO1,C11,C21,C32;clock=H1*H2*H7*H10 OK} {path1=C01,C12,C51;clock=H1*H3 OK path2= C01,C11,C22,C31,C41,C51;clock=H1*H2*H7*H9*H9 OK path3= C01,C11,C22,C42,C51;clock=H1*H2*H6*H8 OK path4= C01,C11,C22,C31,C42,C51;clock=H1*H2*H7*H9*H8 OK path5= CO1,C11,C21,C32,C42,C51;clock=H1*H2*H7*H10*H8 OK}} Clock Calculation for each Path STOP

ISSS ’98 University of Rennes I IFSIC / IRISA C.Wolinski C42 CCFG Start end H1 H3 H2 H7 H10 H9 H6 H9 H8 H1 N3 N0 N1 N2 N4 N5 N6 C01 C41 C22 C21 C32 C31 C42 C51 C12 C11 CCFG Start end H1 H3 H2 H7 H10 H9 H6 H9 H8 H1 N3 N0 N1 N2 N4 N5 N6 C01 C41 C22 C21 C32 C31 C51 C12 C11 JIAN Benchmark Results :

ISSS ’98 University of Rennes I IFSIC / IRISA C.Wolinski