Under Embargo until December 10, 2007 Introducing Cypress West Bridge™Astoria TM.

Slides:



Advertisements
Similar presentations
Computer Architecture
Advertisements

3D Graphics Content Over OCP Martti Venell Sr. Verification Engineer Bitboys.
Interfacing mixed signal peripherals by protocols of packet type Emil Gueorguiev Saramov Angel Nikolaev Popov Computer Systems Department, Technical University.
FX to FX2: A Comparison. Agenda Block diagram Evolution Hardware Firmware Wrap-up.
Flash storage memory and Design Trade offs for SSD performance
PowerEdge T20 Customer Presentation. Product overview Customer benefits Use cases Summary PowerEdge T20 Overview 2 PowerEdge T20 mini tower server.
Thank you for your introduction.
New Solutions to New Threats. The Threats, They Are A Changing Page 2 | © 2008 Palo Alto Networks. Proprietary and Confidential.
StreamBlade SOE TM Initial StreamBlade TM Stream Offload Engine (SOE) Single Board Computer SOE-4-PCI Rev 1.2.
STM32F10x Changes v1.5 to 1.4 HD added Changes v1.4 to 1.3
SOM-5890 Sales Kit Intel® 2 nd Generation Core TM i COM-Express CPU Module EmCore / SOM James Wang Feb. 20, 2011.
0 秘 Type of NAND FLASH Discuss the Differences between Flash NAND Technologies: SLC :Single Level Chip MLC: Multi Level Chip TLC: Tri Level Chip Discuss:
Lowest power 1.8 V audio codec with integrated miniDSP in production today Luca Cacioli Audio Product Marketing Embargoed Until Oct. 27, 2008.
USB Digital Audio Player Using ST92163 By Microcontroller DivisionVersion 1.2 / November 2000.
Zheming CSCE715.  A wireless sensor network (WSN) ◦ Spatially distributed sensors to monitor physical or environmental conditions, and to cooperatively.
IO Controller Module Arbitrates IO from the CCP Physically separable from CCP –Can be used as independent data logger or used in future projects. Implemented.
Computer ArchitectureFall 2008 © November 12, 2007 Nael Abu-Ghazaleh Lecture 24 Disk IO.
Reliable Data Storage using Reed Solomon Code Supervised by: Isaschar (Zigi) Walter Performed by: Ilan Rosenfeld, Moshe Karl Spring 2004 Midterm Presentation.
®. Founded in 1991 Industry Leader: Offers industry’s widest range of programming solutions including: low- cost Universal programmers, High performance.
May 17, Design Option Trade-Offs w Transceiver Design - Dr. Zong Liang Wu, Philips.
Dean A. Klein VP Market Development Micron Technology, Inc.
PHY 201 (Blum) Buses Warning: some of the terminology is used inconsistently within the field.
Peripheral Buses COMP Jamie Curtis. PC Buses ISA is the first generation bus 8 bit on IBM XT 16 bit on 286 or above (16MB/s) Extended through.
May 9, USB 2.0 High Bandwidth Peripheral Design Challenges Robert Shaw Cypress Semiconductor Robert Shaw Cypress Semiconductor
USB Flash Card Writer Using ST92163 By Microcontroller DivisionVersion 1.2 / November 2000.
Peripheral Busses COMP Jamie Curtis. PC Busses ISA is the first generation bus 8 bit on IBM XT 16 bit on 286 or above (16MB/s) Extended through.
Using the PSoC USB March 17, 2012 Lloyd Moore, President/Owner.
Mark Recoskie November 14, Agenda  Quick review of value proposition  Review of Warp r1v2 hardware and software  What’s new in Warp 3.0 hardware?
October 10, USB 2.0 Peripheral Design Options Dave Podsiadlo Product Marketing Manager Cypress Semiconductor Single-Chip, Internal.
Computer Processing of Data
Multimedia & Communications ATMEL Bluetooth Background information on Bluetooth technology ATMEL implementation of Bluetooth spec.
Buses Warning: some of the terminology is used inconsistently within the field.
SPCA554A Mobile Camera Multimedia Processor By Harrison Tsou.
Multimedia Card The Multimedia Card (MMC) is a flash memory memory card standard. MMC cards are currently available in sizes up to and including.
2010 IEEE ICECS - Athens, Greece, December1 Using Flash memories as SIMO channels for extending the lifetime of Solid-State Drives Maria Varsamou.
File Systems in Real-Time Embedded Applications March 7th Eric Julien Choosing the Right Storage Media 1.
Owner: SKRG Rev *A Tech lead: EWOO 1Mb Quad SPI nvSRAM Quick Presentation 1 Quick Presentation: 1Mb Quad SPI nvSRAM Eliminate Batteries and Reduce.
Designing with External Flash Memory on Renesas Platforms
Cypress Confidential Owner: VBHU Sales Training 03/15/2013 Everspin MR4A16B vs. Cypress 16Mb NVSRAM High Frequency Parallel NVSRAM with Multiple Interface.
Owner: ABVY (SKRG, OHP, DCN, GHR, DSG, GMRL, JMY) Synchronous SRAM With On-Chip ECC Quick Presentation Rev **Tech Lead: SKRG 1 High-Performance,
ATtiny23131 A SEMINAR ON AVR MICROCONTROLLER ATtiny2313.
Mass Data Management for Embedded Systems: Compact Flash Eric Ng, MSME EE281: ESDL December 4, 2002.
Architecture of Microprocessor
Quick Presentation: 128Mb to 1Gb Quad SPI FL-S NOR Flash Family FL-S = Cypress’s 3.0-V, 65-nm NOR Flash Memory Family With MirrorBit®1 Technology The.
5 USB Generations ~ 9.25 Hours ~ 14 mins ~ 70 sec ~ 35 sec (LS) (FS)
Quad-Stream AC2350 WiFi ( Mbps) Next generation Wave 2 WiFi Fastest Processor: 1.4 GHz dual core processor Dynamic QoS: Prioritization and bandwidth.
Lecture on Central Process Unit (CPU)
Proposal for an Open Source Flash Failure Analysis Platform (FLAP) By Michael Tomer, Cory Shirts, SzeHsiang Harper, Jake Johns
System Bus.
Contemporary DRAM memories and optimization of their usage Nebojša Milenković and Vladimir Stanković, Faculty of Electronic Engineering, Niš.
Amdahl’s Law & I/O Control Method 1. Amdahl’s Law The overall performance of a system is a result of the interaction of all of its components. System.
Copyright © 2010 Hitachi Data Systems. All rights reserved. Confidential – NDA Strictly Required Hitachi Storage Solutions Hitachi HDD Directions HDD Actual.
IRIS Active Source Workshop Jan 29, 2014 Tucson AZ 125 Texan Recorder Data Storage.
1 Paolo Bianco Storage Architect Sun Microsystems An overview on Hybrid Storage Technologies.
1.3 What Is in There?.  Memory  Hard disk drive  Motherboard  CPU.
1 © 2016 Samsung Electronics America - Confidential Introducing MagicInfo Lite I 4.0.
2D-Graphic Accelerator
M P100.
i.MX Processor Roadmap i.MX 8 family i.MX 8M family i.MX 8X family
FX3S RAID-on-Chip for Server Virtualization
Understanding Modern Flash Memory Systems
What you should know about Flash Storage
USB The topics covered, in order, are USB background
SDM5A-M 7P/180D LP2(H).
Cypress Automotive Flash Roadmap (NDA)
Flash Disk Technology Stop the Spin!
The performance requirements for DSP applications continue to grow and the traditional solutions do not adequately address this new challenge Paradigm.
Quick Presentation: 16Mb Asynchronous SRAM with ECC ECC = Error-Correcting Code New High-Speed, Low-Power Asynchronous SRAMs With On-Chip ECC to Improve.
SM
Presentation transcript:

Under Embargo until December 10, 2007 Introducing Cypress West Bridge™Astoria TM

2 - Cypress Confidential – Agenda West Bridge™ Family Architecture West Bridge™ Antioch System Solution MLC NAND Flash Market Analysis West Bridge™ Astoria™ System Solution

3 - Cypress Confidential – Emb. CPU Embedded World From North & South to West Bridge™ West Bridge CPU North Bridge South Bridge Memory Peripherals PC World

4 - Cypress Confidential – West Bridge Value Proposition Emb. CPU Peripherals Complement functionality of main CPU Enable connectivity to next-generation peripherals and memory High Performance, optimized path for specific applications Offload main CPU from data-intensive operations Bridge to latest interfaces standards Direct connection between peripherals

5 - Cypress Confidential – West Bridge Value Proposition Emb. CPU Peripherals Peripheral controller enabling new interfaces Improves system performance and offload main CPU West Bridge™

6 - Cypress Confidential – West Bridge – One Year Later Smart PhonesData Cards Millions units shipped already and 20+ designs in progress Multimedia Phones

7 - Cypress Confidential – West Bridge™Antioch™ Combined USB and Mass Storage Controller One Year Ago - Antioch

8 - Cypress Confidential – Baseband Processor Multimedia Phone Market Need 3. Dedicated path from USB to Storage 2. High-Speed USB for PC Data Mass Storage 1. High-Density Storage Support

9 - Cypress Confidential – Antioch Performance Comparison Download time for 1GB of data (in seconds) t 9 x 7 x 1 x 32 x 6 x 7 min 1 sec 5 min 35 sec 57s 8 min 37 sec 30 min 29 sec 1 Gigabyte in under 1 min !

10 - Cypress Confidential – MLC NAND Market Analysis

11 - Cypress Confidential – Storage Density Demand Evolution Source: Gartner Research Report 2007

12 - Cypress Confidential – NAND Flash Cost Trends Cost/GB Date SLC NAND MLC NAND $10.00 $7.00 $13.70 $ Year Ago Today Source: DRAMeXchange Nov 2007

13 - Cypress Confidential – Goal: Lower System NAND Costs MPU 1 GB SLC NAND MPU 1 GB MLC NAND $13.70 $4.70

14 - Cypress Confidential – MLC NAND Design Challenges Detect Bits (ECC) Process Technology (nm) MLC SLC 9x 7x 5x 4x Error Correction Requirements Complex NAND Management Complexity increasing with Tech Higher ECC requirement Bad block Management Wear leveling Performance is a challenge Performance goes down with Tech Needs creative Interleaving schemes No Standard NAND I/Fs varies with NAND vendors Vendor-specific optimized commands Timing varies with vendors

15 - Cypress Confidential – West Bridge™Astoria™ Multimedia Mass Storage Controller

16 - Cypress Confidential – Introducing Cypress N-Xpress TM Technology N-Xpress TM Wear Leveling 4-bit Error Correction Coding Bad Block Management Dynamic Interleaving ……. Full NAND Management 4-bit RS ECC Bad block management Wear leveling Dynamic Interleaving Connect up to 16 NANDs High performance throughput Support Lowest Cost NAND Support all NAND vendors Supports all densities Same processor interface

17 - Cypress Confidential – Astoria: Configurable Storage Interface …… Up to 16 MLC NAND MPU Cypress N-Xpress TM Engine SD/MMC & SDIO Engine Configurable Storage Interface Adds SDIO devices and storage at once Astoria TM

18 - Cypress Confidential – Astoria: Flexible Processor Interface …… Up to 16 MLC NAND MPU Cypress N-Xpress TM Engine SD/MMC & SDIO Engine Configurable Storage Interface Flexible Proc. I/F Connect to any Embedded MPU Astoria TM

19 - Cypress Confidential – Astoria: West Bridge SLIM Architecture …… Up to 16 MLC NAND MPU Cypress N-Xpress TM Engine SD/MMC & SDIO Engine Configurable Storage Interface Flexible Proc. I/F USB 2.0 SIE & XCVR Astoria TM SLIM TM Full Multitasking and HS-USB Support

20 - Cypress Confidential – West Bridge Astoria Cypress N-Xpress TM technology Full MLC NAND management Dynamic interleaving over up to 16 devices Support all NAND vendors Latest mass storage interface support Removable storage : SDHC, MMC+, SDIO Embedded storage : MLC NAND, HDD (CE-ATA) Flexible µP interface Async and Sync. SRAM, SPI, ADMUX, NAND Hi-Speed USB support USB 2.0 compliant at 480Mbps 16 configurable endpoints SLIM™ architecture Independent data paths among PC, Storage and µP Dedicated path from PC to mass storage Low Power and space-saving solution 26MHz, 19.2MHz clock input support Small foot-print (6mm x 6mm,.5mm pitch vfBGA) 4 programmable low-power modes

21 - Cypress Confidential – Availability Sampling now Full production H1 2008

22 - Cypress Confidential – Expanding West Bridge World West Bridge Antioch West Bridge Astoria Next Gen. West Bridge …………