A True-Zero Load Stable Capacitor-Free CMOS Low Drop-out Regulator with Excessive Gain Reduction A True-Zero Load Stable Capacitor-Free CMOS Low Drop-out Regulator with Excessive Gain Reduction 1 John Hu and Mohammed Ismail The Analog VLSI Laboratory The Ohio State University Presented at ICECS 2010 December 15, 2010

Outline  Introduction  Issue: Capacitor-Free Low Drop-Out (LDO)  Problem: True-Zero Load Stability  Approach  Method: Excessive Gain Reduction  Schematic Design  Results  Simulations  Measurements  Conclusion 2

Capacitor-Free LDO Regulator  External capacitor-free low drop-out (LDO) regulators are popular because of the benefit in space and cost 3 iPhone 3G, iPhone 4, 2010.

True Zero-Load Stability  Conventional Miller-based pole splitting topologies suffer from zero-load oscillation  There is a short-cut solution: requiring a minimum Iout  Drawbacks  Standby efficiency degradation 4

Proposed Method  Observation: not all DC gain contributes to Miller Effect  Excessive Gain (G1) Reduction  Given the same total DC gain, more can be distributed to G2 and G3 to enhance the Miller effect 5

Schematic Design  Conventional:  G1: opamp  G2: positive gain stage  G3: MPT  Proposed:  G1’  G2’: positive gain stage  G3’: MPT 6

Simulations: Bode Plot 7

Simulations: Load Transient  Load Regulation: (conventional vs. proposed)  Both are stable when power is unlimited  Only the proposed is stable during true zero-load (sleep mode) 8

Conclusion from Simulations Conclusion from Simulations  Power Efficiency Improvement  When true zero-load stability (TZLS) is required (sleep mode), the proposed method reduces the battery current by 67.5% [2]  Area efficiency  Conventional: 23 pF to achieve true zero-load stability [3]  Proposed: 4.5 pF [4] 9

Chip Fabrication  A dual-core LDO was fabricated in MOSIS 0.5 um CMOS under the same specs  One conventional, one proposed. 10

Test Board  PCB with off-chip load test solutions  High power rating resistors, NMOS, “stay alive” Ioutmin options: 11

Test Setup  Test Equipment and Connections 12

Measurement Results  Transient load regulation (conventional):  Vin=3.7 V, Vout=3.5 V. Stability with “stay alive” current. 13

Measurement Results  Transient load regulation:  50% chance of over current (Iout > 1 A, chip heats up.)  Reason: gate of the PMOS pass element floating: top level layout error  Correlation with simulation 14

Conclusion  Conclusions  A true zero-load stable CMOS capacitor-free low drop- out regulator is presented  It reduces the excessive gain (G1) and re-distributes the gain to Miller-enhancing stages (G2, G3)  As a result, system power efficiency during standby can be improved by 67.5%  Future Work  Further analysis of the excessive gain reduction technique and battery life extending IC design methods  Lessons learned for future first-time-right silicon 15

Selected References 1.K. N. Leung and P. Mok, “A capacitor-free CMOS low- dropout regulator with damping-factor-control frequency compensation”, IEEE J. Solid-State Circuits, vol. 38, no. 10, pp , Oct S. K. Lau, P. K. T. Mok, and K. N. Leung, “A low-dropout regulator for SoC with Q-reduction”, IEEE J. Solid-State Circuits, vol. 42, no. 3, pp , Mar R. Milliken, J. Silva-Martinez, and E. Sanchez-Sincencio, “Full on-chip CMOS low-dropout voltage regulator”, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, no.9, pp , Sep J. Hu, W. Liu, and M. Ismail, “Sleep-mode ready, area- efficient capacitor-free low-dropout regulator with input current-differencing”, Analog Integrated Circuits and Signal Processing, vol. 63, no.1, pp , Apr

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