BASIC BLOCKS : PASSIVE COMPONENTS 1

PASSIVE COMPONENTS: Capacitors  Junction Capacitors  Inversion Capacitors  Parallel Plate Capacitors Resistors  Poly Resistors  Diffused Resistors  Switched capacitors as resistors  Active Load 2

CAPACITORS The desired characteristics for capacitors used are given below: · Good matching accuracy · Low voltage-coefficient · High ratio of desired capacitance to Parasitic capacitance · High capacitance per unit area 3

This structure uses the Gate to Source and gate to Drain Capacitances to realise the required Capacitances. This capacitance achieves a large capacitance per unit area and good matching but suffers from high voltage dependent parasitic capacitance to ground. Poly- SiO 2 – Channel Capacitance 4

Poly – SiO 2 – Poly Capacitor This is one of the best configurations for high performance capacitors. 5

MOS Accumulation Capacitor This has a high capacitance per unit area and used where grounded capacitors re required. 6

Capacitors realized using various inter connect layers This gives the method to obtain capacitors by appropriate choice of plates and connection between various metal and Poly Si layers available. It should be mentioned that each interconnect layer is insulated from the others by a SiO 2 layer. Of the various structure shown, the four layer structure has the least parasitic capacitance. 7

As processes migrate toward finer line widths and higher speed performance, the oxide between metals increases while the allowed space between metals decreases. For such processes, samelayer, horizontal, capacitors can be more efficient than different-layer vertical capacitors. This is due to the fact that the allowed space between two M1 lines, for example, is less than the vertical space between M1 and M2. 8

The capacitor plate with the smallest parasitic associated with it is referred to as the top plate. It is not necessarily physically the top plate although quite often it is. In contrast, the bottom plate is that plate having the larger parasitic capacitance associated with it. Schematically, the top plate is represented by the flat plate in the capacitor symbol while the curved plate represents the bottom plate. 9

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While designing for matched capcitors or ratioed capacitors, a technique of common centroid lay out is used. The concept is best illustrated with an example. 11

VICINITY EFFECTS 12

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RESISTORS The diffused resistor is normally formed with source/drain diffusion. The sheet resistance of such resistors are normally in the range of 50 to 100  / for non salicide process and about 5-15  / for sallicide processes. These resistance have a voltage dependence in the range of ppm/V range and also a high parasitic capacitance to ground. 14

The poly Si resistor has a sheet resistance in the range of  / depending on the doping of the poly Si layer. For a polysilicide process the resistance is about 10  /. 15

The n-well resistance has a resistance of 1-10K  / along with a high voltage sensitivity. In cases where accuracy is of no concern this structure is very useful. 16

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ACTIVE (ac) RESISTORS 18

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SWITCHED CAPACITOR RESISTOR 20

AMPLIFIERS 21

SMALL SIGNAL PARAMETERS 22

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COMMON SOURCE AMPLIFIERS 24

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g m = g m1 and R L = R || l r ds1 for Resistance load amplifier g m = g m1 and R L = r ds1 || l r ds2 || l 1/g m2 for Active load amplifier g m = g m1 and R L = r ds1 || l r ds2 for Current source load amplifier and g m = g m1 + g m2 and R L = r ds1 || l r ds2 for Push Pull Amplifier. 26

A in = g m1 (R || l r ds1 ) for Resistance load amplifier A in = g m1 (r ds1 || l r ds2 || l 1/g m2 ) = for Active load amplifier. A in =g m1 (r ds1 || l r ds2 ) = for Current source load amplifier A in =(g m1 + g m2 ) (r ds1 || l r ds2 ) = for Push Pull amplifier. 27

The capacitor at the input C IN = C GS1 for Active Load and Current Source Load Amplifier and C IN = C GS1 + C GS2 for the Push Pull amplifier. The bridging capacitor C = C GD1 for Active Load and Current Source Load Amplifier and C = C GD1 + C GD2 for the Push Pull amplifier. The capacitor at the output C L = C Load + C GS2 + C BD1 + C BD2 for the Active Load amplifier and is C L = C Load + C BD1 + C BD2 for the Current Source Load and Push Pull Amplifiers. 28

C M is the Miller Capacitance seen at the input. 29

COMMON DRAIN AMPLIFIER 30

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COMMON GATE AMPLIFIER 33

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CASCODE AMPLIFIER C 1 = C gd1, C 2 = C db1 + C sb2 + C gs1, C 3 = C gd2 + C db3 + C db2 + C gd3 and  2 = g mbs2 /g m2. 35

Since in the presence of a signal source with a source impedance R S, the pole contributed by the Miller Capacitance seen by the Cascode amplifier will be farther than the Common Source Amplifier with nearly the same gain and input and output impedances. 36

In cascode amplifier we have used a simple current source load. However, to obtain a larger gain we can use a cascade of current mirror load. It should be mentioned here that a single current source is represented as a single transistor with a bias while we have represented a cascade current source with two transistors in series with appropriate gate bias. 37

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g m2 ≈ g m3, g ds2 = g ds3 = g ds1 = g ds5 TELESCOPIC CASCODE AMPLIFIER 39

|| l 1/g ds5 FOLDED CASCODE AMPLIFIER 40