Fast Timing Workshop Krakow, Nov 29 - Dec 1 st 2010 Part 2a

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6 Design Choices Input coupling – Differential versus single-ended input – Needed analog bandwidth – Gain needed? Sampling Options – On ‐ chip PLL/DLL – External DLL – Analog transfer vs interrogate in situ ADC and readout options ADC and readout options – Sequential output select vs random access – On ‐ chip vs. off ‐ chip ADC – Serial, parallel, massively parallel

7 Gary Varner Constraints - Analog Bandwidth - Switching noise - Leakage current - Deeper sampling Extensive radio array for UHE neutrinos - Super B Factory PID Upgrade – precision timing

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16 Gary Varner IRS/Blab3 chips

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18 Gary Varner Blab 1

19 Gary Varner Blab1 chip

20 Gary Varner (IRS chip)

21 Gary Varner (Belle2 Upgrade)

22 Gary Varner HPK SL10

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25 Miroslav Firlej, Jakub Moron, Marek Idzik AGH University, Poland (University for Mining)

26 Miroslav Firlej, Jakub Moron, Marek Idzik

27 Miroslav Firlej, Jakub Moron, Marek Idzik

28 Miroslav Firlej, Jakub Moron, Marek Idzik

29 Miroslav Firlej, Jakub Moron, Marek Idzik

30 Gary Varner, Kurtis Nishimura, Matt Andrew First detector and DAQ test results from the Univ Hawaii picosecond xray beamline FEL = very tight bunch specs ~ 1ps timing probe

31 Gary Varner, Kurtis Nishimura, Matt Andrew

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34 Gary Varner, Kurtis Nishimura, Matt Andrew Phase II: Tunable, mono ‐ chromatic x ‐ ray Source Stabilized optical storage cavity Tests of new detectors: 3D, new chips

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36 Gary Varner, Kurtis Nishimura, Matt Andrew

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