Using emulation for RTL performance verification June 4, 2014 DaeSeo Cha Infrastructure Design Center System LSI Division Samsung Electronics Co., Ltd.

Current Performance Verification System Requirement Architectural Performance Exploration SystemC model, real workload aware performance analysis System Architecture Specification Architectural Performance Verification System C model  Inaccuracy RTL Integration RTL Performance Verification Subsystems/full chip using logic simulation  Slow FPGA RTL Performance Verification Sub-system only  Capacity Post-Silicon RTL Performance Verification Full chip  Too late in development stage

New Approach for Performance Verification System Requirement UVM Testebench System Architecture Specification Big capacity Full chip Accurate Cycle Accuracy Fast 100X+ RTL Integration log log log log Fast Analysis Correlation/Compare Early Stage RTL freeze FPGA GUI Analysis Environment (PRISM) * PRISM: Samsung In-house Tool Summary Post-Silicon Fast and Accurate Performance Verification

Performance Verification Platform Environment Reuse existing UVM simulation environment without any modification Add PV(Performance Verification) components PV components Monitor: Collect various performance metrics Traffic Generator: Random or replay RTL IP’s traffic

UVM Co-emulation Environment UVM Architecture for Co-emulation Simulation environment Incremental elaboration having primary, incremental snapshot Building test scenarios by combining testbench and design in full-chip Emulation environment DUT runs in emulator, incremental elaboration scheme used in emulator UVM testbench Simulator sw_top prim_top tb_top Incr_top Bus UVC AXI bus Module Test scenario hw_top DUT Emulator Register Model Interface Virtual sequencer Interface Sequence REG2BUS adapter DUT Register predictor Interrupt

Performance Monitor -1/2 Performance Metrics Latency: Min/Max/Average, time-varying, accumulated, distributed Bandwidth: Min/Max/Average, time-varying, accumulated, distributed Utilization: Min/Max/Average, time-varying, accumulated, distributed Address pattern Response time Customized metrics like IP’s internal signals (FIFO level) Implementation Synthesizable code for both simulation and emulation Collect performance metrics on AXI interface Issue Run-time overhead in emulation  Synchronization overhead between emulator and simulator PM Log file PRISM PM: performance monitor

Performance Monitor – 2/2 Experiments PV results should be recorded in-order Many experiments are done to reduce run-time overhead GFIFO Transactions are collected in order, it is congruent with the SW simulation Parallel execution of monitor transaction in SW  Improve performance Method Description tbcall sync Overhead No PV Monitor Baseline 398 - $display Sync with TB using $fdisplay() 32,798 81X GFIFO Buffering monitored transaction Collecting process in back ground 472 1.12X bit a; bit [5:0] b; int c; function void my_mon(bit x1, bit [5:0] x2, int x3); $fdisplay(“%d %d %d”, x1, x2, x3); endfunction; initial $ixc_ctrl("gfifo", “my_mon"); always @(clk) begin my_mon(a, b, c) end bit a; bit [5:0] b; int c; always @(clk) begin $fdisplay (“ %d %d %d”, a, b, c); end Simulation Monitor GFIFO

Performance Analysis Environment PRISM (Performance Visualization System) Charting PV results in GUI Easy to find a performance issue by viewing PV results in a single GUI

Experimental Result Application Run-time speed Bugs found Multimedia test scenarios such as video playback, camera recording Run-time speed +100x faster than simulation Bugs found Critical bugs and design weak points which would not been detected during simulation-based verification

Conclusion PV using emulator is a mainstream solution Future Work Very fast bring up using UVM Co-emulation Reusing UVM full-chip testbench without any modification PV in early design development stage with cycle accuracy +100x faster speed compared with simulation approach Efficient PV analysis by PRISM Future Work Add more features to PRISM - correlation, smart PV report etc. Develop ACE PV Monitor for dealing with cache-coherency Deploy UVM Co-emulation for other test scenarios

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