5.4 Decoders A decoder is a multiple-input, multiple-output logic circuit that converts coded inputs into coded outputs, where the input and output codes are different. The input code generally has fewer bits than the output code, and there is one-to-one mapping from input code words into output code words. input code word output enable inputs map Decoder Return Next

5.4 Decoders Binary decoder The most common decoder circuit is an n-to-2n decoder or binary decoder. Such a decoder has an n-bit binary input code and a 1-out-of-2n output code. Truth table for a 2-to-4 binary decoder 2-to-4 Decoder I0 Y0 I1 Y1 Y2 EN Y3 Inputs Outputs EN I1 I0 Y3 Y2 Y1 Y0 0 X X 1 0 0 1 0 1 1 1 0 1 1 1 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 ”don’t-care” notation Return Back Next

5.4 Decoders Simulation Return Back Next

5.4 Decoders It is not necessary to use all of the outputs of a decoder, or even to decode all possible input combinations, e.g. a decimal or BCD decoder. Logic Symbols for Lager-Scale Elements The most basic rule is that logic symbols are drawn with inputs on the left and outputs on the right. The top and bottom edges of a logic symbol are not normally used for signal connections. However, explicit power and ground connections are sometimes shown at the top and bottom, especially if these connections are made on “nonstandard” pins. Return Back Next

5.4 Decoders We use an inversion bubble to indicate an active-low pin and the absence of a bubble to indicate an active-high pin. Active-high pins are given the same name as the internal signal, while active-low pins have the internal signal name with an overbar. external pin 1/2 74X139 G Y0 Y1 A Y2 B Y3 internal signal Return Back Next

Truth table for one-half of a 74x139 dual 2-to-4 decoder 5.4 Decoders The 74x139 Dual 2-to-4 Decoder 1G 1Y0 1Y1 1A 1Y2 1B 1Y3 2G 2Y0 2Y1 2A 2Y2 2B 2Y3 74X139 1 2 3 15 14 13 4 5 6 7 12 11 10 9 1 1 1 1 1 1 1 0 1 1 0 1 1 0 1 1 0 1 1 1 1 X X 0 0 0 0 0 1 0 1 0 0 1 1 Y3 Y2 Y1 Y0 G B A Outputs Inputs Truth table for one-half of a 74x139 dual 2-to-4 decoder ( Logic diagram see P355 Figure 5-35 ) Return Back Next

5.4 Decoders The 74x138 3-to-8 Decoder 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 X X X X X X 1 X X X X X X 1 X X X 1 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 1 1 1 0 0 1 0 0 1 0 0 1 0 1 1 0 0 1 1 0 1 0 0 1 1 1 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 G1 G2A G2B C B A Outputs Inputs ( Logic diagram see P358 Figure 5-37) Return Back Next

5.4 Decoders It has three enable inputs, G1, G2A, G2B , all of which must be asserted for the selected output to be asserted. The equation for the internal output signal Y5: The equation for the external output signal Y5: Active-low Return Back Next

5.4 Decoders Traditional logic symbol of the 74x138 74X138 G1 Y0 6 G1 Y0 G2A Y1 G2B Y2 Y3 Y4 A Y5 B Y6 C Y7 74X138 2 3 15 14 13 12 11 10 9 7 4 5 Return Back Next

5.4 Decoders Cascading Binary Decoders 1 6 G1 Y0 G2A Y1 G2B Y2 Y3 Y4 A Y5 B Y6 C Y7 74X138 2 3 15 14 13 12 11 10 9 7 4 5 N0 N1 N2 N3 DEC0 DEC1 DEC2 DEC3 DEC4 DEC5 DEC6 DEC7 DEC8 DEC9 DEC10 DEC11 DEC12 DEC13 DEC14 DEC15 U1 U2 +5V R The top decoder (U1) is enabled when N3 is 0, and the bottom one (U2) is enabled when N3 is 1. Return Back Next

5.4 Decoders Seven-Segment Decoders a b c d e f g Seven-segment display normally uses light-emitting diodes(LEDs) or liquid-crystal display(LCD) elements. A seven-segment decoder has 4-bit BCD as its input code and the “seven-segment code” 5 4 a BI b c A d B e C f D g 74X49 1 2 6 9 13 8 11 10 12 3 Truth table for a 74x49 seven-segment decoder(See P374 table 5-21) Logic diagram for a 74x49 seven-segment decoder(See P373 figure 5-45 ) Return Back