UTCS CS352, S07 Lecture 10 1 Pipelining Cycle F Instruction RXMW FRXMW FRXMW FRXMW FRXM FRX

UTCS CS352, S07 Lecture 10 2 Pipelined Implementation – add register every t ns I-Mem A DO Reg File RW D-Mem A DO DI IR B A C D E +4 PC

UTCS CS352, S07 Lecture 10 3 Reservation Table for a Simple Pipeline I-Mem A DO Reg File RW D-Mem A DO DI IR B A C D E +4 PC

UTCS CS352, S07 Lecture 10 4 Single Cycle, Multiple Cycle, vs. Pipeline Clk Cycle 1 IfetchRegExecMemWr Cycle 2Cycle 3Cycle 4Cycle 5Cycle 6Cycle 7Cycle 8Cycle 9Cycle 10 LoadIfetchRegExecMemWr IfetchRegExecMem LoadStore IfetchRegExecMemWrStore Clk LoadStoreWaste Ifetch R-type IfetchRegExecMemWrR-type Cycle 1Cycle 2 Multiple Cycle Implementation: Pipeline Implementation: Single Cycle Implementation: Slide courtesy of D. Patterson

UTCS CS352, S07 Lecture 10 5 Why Pipeline? Because the resources are there! I n s t r. O r d e r Time (clock cycles) Inst 0 Inst 1 Inst 2 Inst 4 Inst 3 ALU Im Reg DmReg ALU Im Reg DmReg ALU Im Reg DmReg ALU Im Reg DmReg ALU Im Reg DmReg Slide courtesy of D. Patterson

UTCS CS352, S07 Lecture 10 6 Benefits of Pipelining Before pipelining: –Throughput: 1 instruction per cycle – (or lower cycle time and CPI=5) After pipelining (multiple instructions in pipe at one time) –Throughput: 1 instruction per cycle

UTCS CS352, S07 Lecture 10 7 Pipelining Rules Forward travelling signals at each stage are latched Only perform logic on signals in the same stage –signal labeling useful to prevent errors, e.g., IR R, IR A, IR M, IR W Backward travelling signals at each stage represent hazards

UTCS CS352, S07 Lecture 10 8 Data Hazards (RAW) Cycle F Instruction RXMW FRXMW Write Data to R1 Here Read from R1 Here ADDR1, R2, R3 ADDR4, R1, R5

UTCS CS352, S07 Lecture 10 9 Types of Data Hazards RAW (read after write) –only hazard for fixed pipelines –later instruction must read after earlier instruction writes WAW (write after write) –variable-length pipeline –later instruction must write after earlier instruction writes WAR (write after read) –pipelines with late read –later instruction must write after earlier instruction reads FRAMWFRAMW FR123 FRAMW 4W FR123 FRAMW 4R5W

UTCS CS352, S07 Lecture Control Hazards Cycle F Instruction RXMW FRXMW Destination Available Here Need Destination Here JRR25... XX:ADD...

UTCS CS352, S07 Lecture Resolving Hazards: Pipeline Stalls Can resolve any type of hazard –data, control, or structural Detect the hazard Freeze the pipeline up to the dependent stage until the hazard is resolved

UTCS CS352, S07 Lecture Example Pipeline Stall (Diagram) Cycle F Instruction RXMW FRXMW Write Data to R1 Here Read from R1 Here ADDR1, R2, R3 ADDR4, R1, R5 Bubble

UTCS CS352, S07 Lecture Resolving Hazards: Bypass (Forwarding) If data is available elsewhere in the pipeline, there is no need to stall Detect condition Bypass (or forward) data directly to the consuming pipeline stage Bypass eliminates stalls for single-cycle operations –reduces longest stall to N-1 cycles for N-cycle operations

UTCS CS352, S07 Lecture Simple Pipeline with Bypass Multiplexers I-Mem A DO Reg File RW D-Mem A DO DI IR B A C D E +4 IP

UTCS CS352, S07 Lecture Data Hazards With Bypassing Cycle F Instruction RXMW FRXMW R1 computed R1 used ADDR1, R2, R3 ADDR4, R1, R5 SUBR5, R1, R6 XORR7, R8, R1 FRXMW FRXMW ADD SUB XOR