Atul Pandey Guido Clemens Marius Sida Mentor Graphics Deutschland Gmbh Arnulfstr 201, Munich, Germany – Coverage Driven Verification for Analog Design Based on UCIS

© 2010 Mentor Graphics Corp. Company Confidential Design Process : Birds Eye View Analog and Digital design process are “similar” and follow same phases

© 2010 Mentor Graphics Corp. Company Confidential Digital Design and Verification Process Product/IP specification Implement Verify entity oqpsk_modulator is port ( signal chip_I : in std_logic; signal chip_Q : in std_logic; signal start : in std_logic; entity oqpsk_modulator is port ( signal chip_I : in std_logic; signal chip_Q : in std_logic; signal start : in std_logic; Coverage db Merged coverage db Coverage analysis o Current coverage status o Coverage holes/Exclusions o Trend analysis o Effective tests o Resource allocation o Report generation TestPlan Coverage db

© 2010 Mentor Graphics Corp. Company Confidential (Current)Analog Design and Verification Process Product/IP specification Implement Verify o What is the current status of the design? o Have we verified all specifications? o Who needs help? o Are we on the right track? o Report for team members/manager More corners means more data to Analyze We’ve got a problem here!

© 2010 Mentor Graphics Corp. Company Confidential Analog Verification Components Analog Verification Nature of Specification  Temporal  Frequency  Yield Parametric Verification  PVT  Regression SPICE (Tool and Language) Waiver/Exclusion Mechanism Pre-Layout verification Post-Layout verification

© 2010 Mentor Graphics Corp. Company Confidential UCIS based CDV for Analog Design Coverage viewer Coverage analysis Coverage report Trend analysis Questa ® SIM - UCIS Framework

© 2010 Mentor Graphics Corp. Company Confidential An Implementation Example OPAMP to be used in LDO in_n in_p out_p vdd vss bias_in op_en

© 2010 Mentor Graphics Corp. Company Confidential Specification of an OPAMP Design for a LDO

© 2010 Mentor Graphics Corp. Company Confidential TestPlan #DescriptionLinkTypeWeightGoalResponse CheckingPriorityResponsible 1AC Analysis Gain is > 70dBgainAssertion1100 atpandey 1.23db bandwidth is > 8k Hz3db_bwAssertion1100spice sim1atpandey 1.3UGB is > 10MhzugbAssertion1100spice sim1atpandey 1.4Phase margin > 60 degph_marginAssertion1100spice sim1atpandey 2Transient analysis SlewRate > 100V/usslewrateAssertion1100spice sim1atpandey 2.2rise_delay -- rise vin to rise vout delay between 1ps and 1ns rise_delayAssertion1100spice sim atpandey 2.3overshoot above logic levelovershootAssertion1100spice sim1atpandey 2.4undershoot below logic levelundershootAssertion1100spice sim1atpandey 2.5Quiescent power in power down mode <1nWqp_pdAssertion1100spice sim1atpandey 2.6Quiescent power in active mode <1uWqp_amdAssertion1100spice sim1atpandey 2.7Max power in active mode <10uWmxp_amdAssertion1100spice sim1atpandey 2.8check on all nmos devices that VDS <1.2ovstress_n_ch eck Assertion1100spice sim1atpandey 2.9check on all pmos devices that VDS <1.2ovstress_p_ch eck Assertion1100spice sim1atpandey 3DC Analysis offset, crossing point at 0, should be less than 5mVoffsetAssertion1100spice sim1atpandey 3.2value of max dc current in dc analysis : upper limit 100u ivdd_maxAssertion1100spice sim1atpandey 3.3max dc power < 10uWmxp_dcAssertion1100spice sim atpandey

© 2010 Mentor Graphics Corp. Company Confidential Waveform postprocessing Coverage db TestPlan Simulation A (ex. Transient) Simulation N (ex. AC,PVT,Yield)

© 2010 Mentor Graphics Corp. Company Confidential Coverage Analysis Coverage status at Later design stage Coverage Status at certain design stage

© 2010 Mentor Graphics Corp. Company Confidential Novel Aspects of this work Compatible coverage based verification between Analog and Digital design verification —Coverage generation and analysis infrastructure is common between Analog and Digital design —Information exchange format is UCIS Unique characteristics of analog design and verification are addressed —Use of existing language and tool for analog design —Can be basis of Regression data Management/Analysis Scalable to most analog designs Design debug information is annotated Extendable to cover Physical Specification/Verification requirements

© 2010 Mentor Graphics Corp. Company Confidential Digital Design Analog Design Coverage viewer Coverage analysis Coverage report Trend analysis Coverage viewer Coverage analysis Coverage report Trend analysis Coverage Driven verification Questions? Executable Process Management and Tracking For Mixed-Signal designs

© 2010 Mentor Graphics Corp. Company Confidential References [1] Alon Gluska: Coverage-Oriented Verification of Banias, Design Automation Conference, Proceedings [2] Andrew Piziali: Functional Verification Coverage Measurement and Analysis; Springer link [3] G. Al Sammane, M.H. Zaki, Z.J. Dong and S. Tahar: Towards Assertion Based Verification of Analog and Mixed Signal Designs Using PSL; Proc. Languages for Formal Specification and Verification, Forum on Specification & Design Languages (FDL'07), Barcelona, Spain, September 2007, pp [4] Unified Coverage Interoperability Standard: [5] Eldo® Reference Manual: online, [6] Questa® SIM User’s Manual: online, [7] UCIS standard 1.0: pdf pdf [8] Willy M. C. Sansen, Measurement of Operational Amplifier Characteristics in the Frequency Domain, IEEE Transactions on Instrumentation and Measurements, Vol. 1M-34, No. I, March 1985

© 2010 Mentor Graphics Corp. Company Confidential Coverage Driven Verification based on UCIS UCIS is an Accellera standard [4] Facilitates interoperability between various coverage sources & tools Standard coverage models for commonly used metrics Extendable to add user defined attributes Used as the basis of coverage infrastructure in this work