VHDL - Introduction.

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Presentation transcript:

VHDL - Introduction

VHDL’s History Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) is the product of a US Government request for a new means of describing digital hardware. The VHSIC Program was an initiative of the Defence Department to push the state of the art in VLSI technology, and VHDL was proposed as a versatile hardware description language.

VHDL’s History (Cont.) The language were first generated in 1981 under the VHSIC program. A number of U.S. companies were involved in designing VHSIC chips for the Department of Defense (DoD). In July 1983, a team of Intermetrics, IBM and Texas Instruments were awarded a contract to develop VHDL In August 1985, the final version of the language under government contract was released: VHDL Version 7.2

VHDL’s History (Cont.) In December 1987, VHDL became IEEE Standard 1076- 1987 and in 1988 an ANSI standard In September 1993, VHDL was restandardized to clarify and enhance the language (IEEE Standard 1076-1993) VHDL has been accepted as a Draft International Standard by the IEC (International Engineering Consortium) .

ELEC2200-002 Lecture 7 (updated) Applications of HDL Model and document digital systems Different levels of abstraction Behavioral, structural, etc. Verify design Synthesize circuits Convert from higher abstraction levels to lower abstraction levels Fall 08, Oct 29 ELEC2200-002 Lecture 7 (updated)

Input-Output specification of circuit Example: my_ckt Inputs: A, B, C Outputs: X, Y VHDL description: entity my_ckt is port ( A: in bit; B: in bit; S: in bit; X: out bit; Y: out bit); end my_ckt ; my_ckt A X B Y S Fall 08, Oct 29 ELEC2200-002 Lecture 7 (updated)

VHDL entity entity my_ckt is port ( A: in bit; B: in bit; S: in bit; X: out bit; Y: out bit ); end my_ckt; Datatypes: In-built User-defined Name of the circuit User-defined Filename same as circuit name recommended Example: Circuit name: my_ckt Filename: my_ckt.vhd Name of the circuit User-defined Filename same as circuit name Example. Circuit name: my_ckt Filename: my_ckt.vhd my_ckt A B S X Y Direction of port 3 main types: in: Input out: Output inout: Bidirectional Port names or Signal names Note the absence of semicolon “;” at the end of the last signal and the presence at the end of the closing bracket Fall 08, Oct 29 ELEC2200-002 Lecture 7 (updated)

ELEC2200-002 Lecture 7 (updated) Built-in Datatypes Scalar (single valued) signal types: bit boolean integer Examples: A: in bit; G: out boolean; K: out integer range -2**4 to 2**4-1; Aggregate (collection) signal types: bit_vector: array of bits representing binary numbers signed: array of bits representing signed binary numbers D: in bit_vector(0 to 7); E: in bit_vector(7 downto 0); M: in signed (4 downto 0); --signed 5 bit_vector binary number Fall 08, Oct 29 ELEC2200-002 Lecture 7 (updated)

User-defined datatype Construct datatypes arbitrarily or using built-in datatypes Examples: type temperature is (high, medium, low); type byte is array(0 to 7) of bit; Fall 08, Oct 29 ELEC2200-002 Lecture 7 (updated)

Functional specification Example: Behavior for output X: When S = 0 X <= A When S = 1 X <= B Behavior for output Y: When X = 0 and S =0 Y <= ‘1’ Else Y <= ‘0’ my_ckt A X B Y S Fall 08, Oct 29 ELEC2200-002 Lecture 7 (updated)

ELEC2200-002 Lecture 7 (updated) VHDL Architecture VHDL description (sequential behavior): architecture arch_name of my_ckt is begin p1: process (A,B,S) begin if (S=‘0’) then X <= A; else X <= B; end if; if ((X = ‘0’) and (S = ‘0’)) then Y <= ‘1’; Y <= ‘0’; end process p1; end; Error: Signals defined as output ports can only be driven and not read Fall 08, Oct 29 ELEC2200-002 Lecture 7 (updated)

ELEC2200-002 Lecture 7 (updated) VHDL Architecture architecture behav_seq of my_ckt is signal Xtmp: bit; begin p1: process (A,B,S,Xtmp) begin if (S=‘0’) then Xtmp <= A; else Xtmp <= B; end if; if ((Xtmp = ‘0’) and (S = ‘0’)) then Y <= ‘1’; Y <= ‘0’; X <= Xtmp; end process p1; end; Signals can only be defined in this place before the begin keyword General rule: Include all signals in the sensitivity list of the process which either appear in relational comparisons or on the right side of the assignment operator inside the process construct. In our example: Xtmp and S occur in relational comparisons A, B and Xtmp occur on the right side of the assignment operators Fall 08, Oct 29 ELEC2200-002 Lecture 7 (updated)

ELEC2200-002 Lecture 7 (updated) VHDL Architecture VHDL description (concurrent behavior): architecture behav_conc of my_ckt is signal Xtmp: bit; begin Xtmp <= A when (S=‘0’) else B; Y <= ‘1’ when ((Xtmp = ‘0’) and (S = ‘0’)) else ‘0’; X <= Xtmp; end ; Fall 08, Oct 29 ELEC2200-002 Lecture 7 (updated)

ELEC2200-002 Lecture 7 (updated) Signals vs Variables Signals Signals follow the notion of ‘event scheduling’ An event is characterized by a (time,value) pair Signal assignment example: X <= Xtmp; means Schedule the assignment of the value of signal Xtmp to signal X at (Current time + delta) where delta: infinitesimal time unit used by simulator for processing the signals Fall 08, Oct 29 ELEC2200-002 Lecture 7 (updated)

ELEC2200-002 Lecture 7 (updated) Signals vs Variables Variables Variables do not have notion of ‘events’ Variables can be defined and used only inside the process block and some other special blocks. Variable declaration and assignment example: process (…) variable K : bit; begin … -- Assign the value of signal L to var. K immediately K := L; end process; Variables can only be defined and used inside the process construct and can be defined only in this place Fall 08, Oct 29 ELEC2200-002 Lecture 7 (updated)

ELEC2200-002 Lecture 7 (updated) Simulation Simulation is modeling the output response of a circuit to given input stimuli For our example circuit: Given the values of A, B and S Determine the values of X and Y Many types of simulators used Event driven simulator is used popularly Simulation tool we shall use: ModelSim my_ckt A X B Y S Fall 08, Oct 29 ELEC2200-002 Lecture 7 (updated)

ELEC2200-002 Lecture 7 (updated) Simulation architecture behav_seq of my_ckt is signal Xtmp: bit; begin p1: process (A,B,S,Xtmp) variable XtmpVar: bit; begin if (S=‘0’) then Xtmp <= A; else Xtmp <= B; end if; if ((Xtmp = ‘0’) and (S = ‘0’)) then Y <= ‘1’; Y <= ‘0’; X <= Xtmp; XtmpVar := Xtmp; end process p1; end; Time ‘T’ A B S Xtmp Y XtmpVar X 0- U ‘X’ 1 0+d 0+2d 1+d 1+2d Scheduled events executed: Xtmp = 0 Y = 0 X = ‘X’ Assignments executed: XtmpVar = 0 Scheduled events executed: Xtmp = 0 Y = 1 X = 0 Scheduled events list: Xtmp = (0,0+d) Y = (0,0+d) X = (‘X’,0+d) Scheduled events list: (empty) Assignments executed: XtmpVar = ‘X’ Scheduled events list: Xtmp = (0,0+2d) Y = (1,0+2d) X = (‘0’,0+2d) Fall 08, Oct 29 ELEC2200-002 Lecture 7 (updated)

ELEC2200-002 Lecture 7 (updated) Synthesis Synthesis: Conversion of behavioral level description to structural level netlist Abstract behavioral description maps to concrete logic-level implementation For ex. Integers at behavioral level mapped to bits at structural level Structural level netlist Implementation of behavioral description Describes interconnection of gates Synthesis tool we shall use: Leonardo Spectrum Fall 08, Oct 29 ELEC2200-002 Lecture 7 (updated)

Structural level netlist Behavior of our example circuit: Behavior for output X: When S = 0 X <= A When S = 1 X <= B Behavior for output Y: When X = 0 and S =0 Y <= 1 Else Y <= 0 my_ckt A X B Y S Logic functions Sbar = ~ S Xbar = ~ X X = A*(Sbar) + B*S Y = (Xbar)*(Sbar) Fall 08, Oct 29 ELEC2200-002 Lecture 7 (updated)

Structural level netlist architecture behav_conc of my_ckt is -- component declarations signal Sbar, Xbar, W1, W2: bit; begin G1: not port map(Sbar,S); G2: and port map(W1,A,Sbar); G3: and port map(W2,B,S); G4: or port map(X,W1,W2); G5: not port map(Xbar,X); G6: and port map(Y,Xbar,Sbar); end ; Gate level VHDL descriptions (and, or, etc) are described separately Design in which other design descriptions are included is called a “hierarchical design” A VHDL design is included in current design using port map statement Fall 08, Oct 29 ELEC2200-002 Lecture 7 (updated)

ELEC2200-002 Lecture 7 (updated) AND GATE Fall 08, Oct 29 ELEC2200-002 Lecture 7 (updated)

ELEC2200-002 Lecture 7 (updated) XOR Fall 08, Oct 29 ELEC2200-002 Lecture 7 (updated)

ELEC2200-002 Lecture 7 (updated) OR GATE Fall 08, Oct 29 ELEC2200-002 Lecture 7 (updated)

ELEC2200-002 Lecture 7 (updated) 4X1 MUX Fall 08, Oct 29 ELEC2200-002 Lecture 7 (updated)

ELEC2200-002 Lecture 7 (updated) Fall 08, Oct 29 ELEC2200-002 Lecture 7 (updated)

ELEC2200-002 Lecture 7 (updated) DECODER 2X4 Fall 08, Oct 29 ELEC2200-002 Lecture 7 (updated)

ELEC2200-002 Lecture 7 (updated) Fall 08, Oct 29 ELEC2200-002 Lecture 7 (updated)

ELEC2200-002 Lecture 7 (updated) Fall 08, Oct 29 ELEC2200-002 Lecture 7 (updated)

ELEC2200-002 Lecture 7 (updated) Fall 08, Oct 29 ELEC2200-002 Lecture 7 (updated)