Hardware Implementation of Simplex Algorithm for Flash ADC Optimization Yuta Toriyama yuta@ee.ucla.edu April 09, 2010

Outline Probabilistic Flash ADC Problem Representing the Flash ADC as a network graph Linear Program & Simplex Algorithm Hardware Implementation Conclusion

Project Goal Goal: Hardware Implementation Simplex Algorithm for use with Flash ADC optimization Accompanies design of ADC for low-power bio-medical applications which could allow for non-uniform quantization Need small devices and/or lower supply voltages Problem: The relative process variability increases IC design today is largely application driven. The applications enforce constraints which thereby influence our design methodologies. Example applications....

Flash ADC Yield Yield: % that measures the proportion of ADCs with correct functionality. Decision levels from V0 to VN are monotonically increasing. 1 1 1 1

Flash ADC Yield Assume a Gaussian pdf: & Solid line – calculated yield X – 10,000 pt. Monte Carlo

Probabilistic Approach Problem: Choose the active comparators Turn off power to non- working comparators Constraints: Maximize SNR Requirements: Threshold values and indexes of chosen comparators must be monotonically increasing Single 1 output to decoder 1 X 1 1 X Logic Encoder X X

Network Formulation of ADC 1 2 3 4 5 6 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 = A nodes arcs

Cost Vector Formulation Calculate the noise power contribution of each arc: Vj Ck = for all k = {1,2,Numarcs} Vi di = 4 Allows for the inclusion of non-uniform distributions

LP Formulation maximize cTx s.t. Ax = [1 0 0 . . .-1]T 0 ≤ xi ≤ 1, i Optimal solution satisfies xi  {0,1} Arcs with xi=1 identify the path from V1 to VN that maximizes the SNR for a given input pdf 1 2 3 4 5 6 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 = A nodes arcs

Simplex Algorithm Simplex algorithm solves the LP very quickly even for large matrices Main operation is series of Gaussian eliminations Things to note: initial matrix setup finding an initial basic feasible solution 1 2 3 4 5 6 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 = A nodes arcs

Simplex Algorithm Simplex algorithm solves the LP very quickly even for large matrices Main operation is series of Gaussian eliminations Things to note: initial matrix setup finding an initial basic feasible solution 1 2 3 4 5 6 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 = A nodes arcs

Simplex Algorithm Simplex algorithm solves the LP very quickly even for large matrices Main operation is series of Gaussian eliminations Things to note: initial matrix setup finding an initial basic feasible solution 1 2 3 4 5 6 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 1 -1 1 -1 1 -1 1 -1 1 -1 = A nodes arcs

Hardware Implementation Realized on IBOB (?) Xilinx Virtex-II Pro 2VP50 FPGA Simulink Xilinx Blockset Given: Decision thresholds of each comparator (Cutoff threshold of arc cost) Needs to: Create the A matrix Create the cost vector Run the Simplex Algorithm Main Issue: Resource Usage

Resource Usage Creating the cost vector requires many additions and multiplications Complexity The matrix we want is huge: N=210 comparators = number of rows Cost cutoff to limit number of columns

Storing the Big Matrix MATLAB simulations of step-by-step simplex algorithm to observe characteristics of matrix Special Characteristics we need to exploit Sparse Only non-zero elements are +1 / -1 Don’t need the xi ≤ 1 constraint maximize cTx Try to balance implementation feasibility and resource usage s.t. Ax = [1 0 0 . . .-1]T 0 ≤ xi ≤ 1, i Store in a compressed format (x, y, sign)

Work in Progress Creation of the A matrix and cost vector have been implemented and put on FPGA To be done: Simplex Algorithm Optimizations (?) Wordlength Timing The Simplex Algorithm is a series of Gaussian eliminations Need to come up with hardware design, given the way the matrix is stored in memory

Conclusions By modeling the system as a network graph, the maximum SNR can be determined using the Simplex method Hardware implementation seems feasible, though ASIC realization is probably impractical

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