HSSD Project Planning Nuno Miguel Cardanha Paulino PDEEC

Implementation Overview Figure 1 – Overview of Local Memory Architecture CPU (Microblaze) Runs application LMB Injector Bus monitor/modifier RPU – Executes CDFGs – No memory accesses

Memory Access Architecture Proposal Enchanced Injector – Explicitly stall the CPU – Bus access multiplexing Loader/Storer – Memory stimuli – Clock gate RPU when FIFOs full – 1 load and 1 store per – Loader scheduling Adapt RPU – Generate/accept data/address at any row, or limit loads/stores to first/last rows – Loader FIFO not empty stall Select memory access benchmarks – Vecsum, dotprod, max Compare speedups with CatapultC Figure 2 – Possible Memory access architecture