Introduction to DDR SDRAM Bill Gervasi Technology Analyst wmgervasi@attbi.com

Topics to Cover The SDRAM Roadmap Transitioning from SDR to DDR DDR-I 400 Overview Market overview

Simple, incremental steps SDRAM Evolution 5400MB/s Mainstream Memories DDR667 4300MB/s DDR533 3200MB/s DDR400 2700MB/s “DDR II” DDR333 2100MB/s DDR400? 3200MB/s DDR266 1600MB/s DDR200 1100MB/s “DDR I” PC133 Simple, incremental steps “SDR”

Key to System Evolution Never over-design! Implement just enough new features to achieve incremental improvements Use low cost high volume infrastructure Processes Packages Printed circuit boards

From SDR to DDR Prefetch 2 Prefetch 2 Differential Clocks Signaling & Power Write Latency When considering migrating a design from SDR to DDR, the five primary factors to consider are signaling, clocks, data strobe, packages, and total pin count. Data Strobe

Prefetch Today’s SDRAM architectures assume an inexpensive DRAM core timing DDR I (DDR200, DDR266, and DDR333) prefetches 2 data bits: increase performance without increasing core timing costs DDR II (DDR400, DDR533, DDR667) prefetches 4 bits internally, but keeps DDR double pumped I/O DDR-I 400 is a prefetch-2 architecture

Prefetch Depth CK data READ Core access time Costs $$$ SDR: Prefetch 1 Core access time DDR-I: Prefetch 2 DDR-II: Prefetch 4 Costs $$$ Column cycle time Essentially free Costs $$$

Prefetch Impact on Cost SDRAM Family Pre- fetch Data Rate Cycle Time High Yield = Affordable 1 100 10 ns SDR 1 133 7.5 ns 2 200 10 ns DDR-I 2 266 7.5 ns Starts to get REAL EXPENSIVE! 2 333 6 ns 2 400 5 ns DDR-II 4 400 10 ns 4 533 7.5 ns Comparable to DDR266 in cost

DDR Data Timing Data valid on rising & falling edges… “Double Data Rate” Source Synchronous; Data Strobe “DQS” travels with data Double data rate signals are sampled at both edges of the clock. Since the clock loading is different from the data loading, it makes a poor choice for a strobe. Hence, a new data strobe signal (DQS) is introduced. DQS is driven by the controller during data write operations, and driven by the SDRAM during data read operations. The DQS signal is loaded exactly like the data lines, therefore exhibits identical electrical characteristics. DDR SDRAMs also provide an on-chip DLL that keeps the delivery of DQS and the data during read operations synchronized to the clock input to the DDR SDRAM. This allows two significant designer choices: operating massive systems like servers with an echo clock, or operating fully synchronous systems that must capture return data in a single clock period. Another enhancement from the user perspective is a guarantee by specification of the width of a data window to insure sufficient time to capture that data. This parameter, tDV, guarantees that jitter will not close the data valid eye.

From SDR to DDR Prefetch 2 Differential Clocks Differential Clocks Signaling & Power Write Latency When considering migrating a design from SDR to DDR, the five primary factors to consider are signaling, clocks, data strobe, packages, and total pin count. Data Strobe

DDR Clocks Differential clocks on adjacent traces Timing is relative to crosspoint Helps ensure 50% duty cycle DDR uses a differential clock in order to deliver a nearly perfect square wave to the DDR SDRAM internal circuits. Running clock and its complement on adjacent traces from controller to the DDR SDRAM enhances signal quality through common mode rejection. For simplicity in reading the diagrams, subsequent drawings will only show the CK signal, but it is understood that this refers to the crosspoint of the clock CK and its complement /CK.

Single Ended Clock VREF CK Clock high time Clock low time VREF CK Normal balanced signal VREF CK Clock high time Clock low time Mismatched Rise & Fall signal Error!

Significantly reduced symmetry error Differential Clock CK CK Clock high time Clock low time Normal balanced signal CK CK Clock high time Clock low time Mismatched Rise & Fall signal Significantly reduced symmetry error

From SDR to DDR Prefetch 2 Differential Clocks Signaling & Power Write Latency When considering migrating a design from SDR to DDR, the five primary factors to consider are signaling, clocks, data strobe, packages, and total pin count. Data Strobe

DDR Signaling SSTL_2 low voltage swing inputs 2.5V I/O with 1.25V reference voltage Low voltage swing with termination Rail to rail if unterminated SSTL_2 signals trigger high and low levels as a few millivolts off a central voltage reference. With simple resistor termination networks to a termination voltage, VTT, equal to the reference voltage, low voltage signaling appears on the transmission lines. If the termination resistors are eliminated, the SSTL_2 signals run rail to rail, with 2.5V swings. Voltage levels for high and low are still recognized and the system operates fine.

Keys to low power design: Power = CV2f%# Factors: Capacitance (C) Voltage (V) Frequency (f) Duty cycle (%) Power states (# circuits in use) Keys to low power design: Reduce C and V Match f to demand Minimize duty cycle Utilize power states

Power: SDR  DDR-I DDR-II DDR533 @ 1.8V DDR266 @ 2.5V PC-133 @ 3.3V

From SDR to DDR Prefetch 2 Differential Clocks Signaling & Power Write Latency When considering migrating a design from SDR to DDR, the five primary factors to consider are signaling, clocks, data strobe, packages, and total pin count. Data Strobe Data Strobe

Emphasis on “Matched” DM/DQS loading identical to DQ CONTROLLER DDR SDRAM DQ/DQS VREF VREF DM VREF A key performance enhancement in DDR comes from thinking of a 64bit bus as eight semi-independent 8bit buses consisting of 8 data lines DQ, one data strobe DQS, and one data mask DM. Within each group of 10 pins, length, loading, and termination should be balanced as accurately as possible. This includes the DM, which though used only for data writes, should have a fake read channel that is never used to insure identical loading to the bidirectional DQ and DQS lines. In this way, controller input circuits will see minimal skew between signals, and can resynchronize all data groups to the internal timing of the controller. VREF Disable DM/DQS loading identical to DQ Route as independent 8bit buses

Copper from controller to SDRAMs Sync to Controller clock 64 = 8 x 8 64bit bus is 8 sync’ed 8bit buses Allows external “copper” flexibility 8 buses resync upon entry to FIFO x16 DDR SDRAM x16 DDR SDRAM x16 DDR SDRAM x16 DDR SDRAM Copper from controller to SDRAMs 8 DQ 1 DM 1 DQS 8 DQ 1 DM 1 DQS 8 DQ 1 DM 1 DQS Inside Controller 8bit Buffer 8bit Buffer Sync to Controller clock 64bit Memory Controller Internal FIFO

From SDR to DDR Prefetch 2 Differential Clocks Signaling & Power Write Latency Write Latency When considering migrating a design from SDR to DDR, the five primary factors to consider are signaling, clocks, data strobe, packages, and total pin count. Data Strobe

Write Latency SDR had to keep inputs powered all the time Adding Write Latency to DDR allowed inputs to be powered off between commands Flexible timing differences on data and address paths

DDR-I vs DDR-II @ 400 “DDR II” “DDR I” 3200MB/s 2700MB/s DDR400 DDR333

DDR-I 400 Summary DDR-I is hard to design to 400 MHz data rate Lower yields No JEDEC standard Prefetch-2, 2.5V signals, TSOP packages, write latency 1 DDR-II makes it a lot easier JEDEC standards & focus Prefetch-4, 1.8V signals, differential strobe On-die termination, BGA packages, write latency > 1 Same plane referencing Few suppliers supporting DDR-I 400 market

DDR-I 400 Conclusion The JEDEC roadmap represents the industry focus for mainstream products DDR-I tops out at 333 MHz data rate DDR-II starts at 400 MHz data rate This DOES NOT mean that DDR-I at 400 MHz data rate will not ship in volume It DOES mean that there will be price premiums for this speed bin

Market Outlook DDR-I DDR-II DDR333 is the mainstream product for 2003 DDR-I 400 will be the premium market DDR-II DDR-II designs under way now DDR-II 400 & 533 will sample in 2003 DDR-II ramp begins in 2004

Summary DDR has many improvements over SDR Prefetch, differential clock, low voltage, data strobe, write latency DDR-I 400 likely to stay a profitable niche DDR-II volume products for 400 & 533 ramp in 2004

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