Mobius Microsystems Microsystems Mbius Slide 1 of 21 A 9.2mW 528/66/50MHz Monolithic Clock Synthesizer for Mobile µP Platforms Custom Integrated Circuits Conference (CICC) 2005 Michael S. McCorquodale, Ph.D. Mobius Microsystems, Inc.

Microsystems Mbius Mobius Microsystems Slide 2 of 21 Outline Introduction Background Clock synthesizer reference oscillator and architecture Experimental results Conclusions and future work

Mobius Microsystems Microsystems Mbius Slide 3 of 21 Introduction

Microsystems Mbius Mobius Microsystems Slide 4 of 21 Introduction Much recent work exploring alternative technologies to XTALs for clock generation and frequency synthesis MEMS microresonators FBAR Insufficient exploration of all-Si CMOS approaches Build on recent work in free-running and open-loop compensation of LC oscillators as frequency references for clock generation

Microsystems Mbius Mobius Microsystems Slide 5 of 21 Introduction Goals Develop an accurate and stable clock synthesizer without an external frequency reference (i.e. XTAL or ceramic resonator) Develop a clock synthesizer with very low frequency scaling latency Develop a clock synthesizer with very low start-up latency Characterize performance over PVT Demonstrate in a multi-chip module Approach Explore free-running RF LC oscillators as frequency references Utilize a top-down synthesis architecture

Mobius Microsystems Microsystems Mbius Slide 6 of 21 Background

Microsystems Mbius Mobius Microsystems Slide 7 of 21 Architecture Reference oscillator Free-running high- Q LC oscillator at a high frequency Simple frequency trimming interface Open loop compensation to stabilize over PVT Very low phase noise Very low start-up latency Clock synthesis Divide down to target clock frequencies Decrease phase noise by 20log 10 ( N ) for divide by N

Microsystems Mbius Mobius Microsystems Slide 8 of 21 Background i icic -gm-gm + _ + _ RLRL L C v + _ RCRC RoRo RoRo t gm0gm0 i(t)i(t) t ic(t)ic(t) Resonant frequency Sources of frequency drift Real losses: R L and R C Frequency modulation from harmonic content of driving amplifier Filter response of LC network and amplifier output resistance

Microsystems Mbius Mobius Microsystems Slide 9 of 21 Background f o vs. g m relationship g mo minimum g m for start-up f o decreases as g m increases (harmonic content increases) f min approached as harmonic content approaches square wave Can utilize harmonic modulation to self-compensate drift by modulating g m through bias current No oscillation fofo gmgm g mo f max f min

Mobius Microsystems Microsystems Mbius Slide 10 of 21 Clock Synthesizer Reference Oscillator and Architecture

Microsystems Mbius Mobius Microsystems Slide 11 of 21 Reference Oscillator v cal R +out 6.1nH pF R out- 50k 300 A MR n MR p m pF 3pF R Complementary cross-coupled architecture with PMOS tail for low phase noise Bias current, temperature dependent and scaled by ~10x in mirror Resistor divider self-biases control voltage and reduces V DD sensitivity v cal trims frequency Reset transistors disable oscillator

Microsystems Mbius Mobius Microsystems Slide 12 of 21 Architecture ÷2 BUF 1 0 ÷8 Out S 1.056GHz 528MHz 66MHz 50MHz v cal EN1 EN0 R ÷10 Top-down or divisive architecture reduces phase noise and period jitter of reference oscillator by 20log 10 ( N ) and sqrt( N ) RF reference oscillator can be started with low latency Any available frequency can be selected asynchronously: low scaling latency

Mobius Microsystems Microsystems Mbius Slide 13 of 21 Experimental Results

Microsystems Mbius Mobius Microsystems Slide 14 of 21 Die Micrograph Fabricated in IBMs 0.18 m 7RF-CMOS process Core macro size: <0.4mm 2 Test macros populate periphery Output drivers drive 10pF with 100ps rise/fall times at 20mA rms Wire-bonded and characterized in 16-pin ceramic DIP Au studs for flip-chip module assembly

Microsystems Mbius Mobius Microsystems Slide 15 of 21 Temperature and Voltage Drift V DD ±10% 25°C: ±0.17% 100°C: ±0.33% Temperature 0 – 70°C: ±0.75% -40 – 100°C: ±1.5% PVT Total Best: <±1% Worst: ~±1.5% Temp. compensation Under-compensated 1.6mV/°C, R 2 =

Microsystems Mbius Mobius Microsystems Slide 16 of 21 Start-up Latency 3.2 s Measured 3.2 s start-up latency from leakage only power state Latency originates primarily from bias start-up time Bias circuitry can be modified to reduce latency to ~ns

Microsystems Mbius Mobius Microsystems Slide 17 of 21 Period Jitter Measured with Agilent Infinium 4GSa/s scope 250k samples per edge 66MHz clock measurement shown RMS jitter determined by removing trigger jitter

Microsystems Mbius Mobius Microsystems Slide 18 of 21 Performance Summary ParameterMeasuredUnit Power supply voltage (nom./min.)1.8/1.12V Power supply current ( V DD = 1.8V/1.12V)5.1/3.5mA Standby power supply current ( V DD = 1.8V)300nA Power dissipation ( V DD = 1.8V)9.2mW Output frequencies 49.5 – – – MHz Frequency calibration (tuning) range±6.2% RMS period jitter (528/66/50 MHz output)7.4/21/33ps Temperature frequency drift (-40 to 100°C)±1.5% Power supply frequency drift ( V DD ±10%)±0.33% Total freq. accuracy (process, voltage, temp.)±1.8% Start-up latency3.2 s

Mobius Microsystems Microsystems Mbius Slide 19 of 21 Conclusions and Future Work

Microsystems Mbius Mobius Microsystems Slide 20 of 21 Conclusions and Future Work Demonstrated a self-referenced LC clock synthesizer with no external reference Low jitter and scaling/start-up latency Low overall drift, though drift under-compensated Temperature compensation correction linear Alternative compensation techniques already in Si Very high total accuracy over PVT to be reported soon Potentially an all-Si approach to stable and accurate clock synthesis Never underestimate what can be done with CMOS alone

Mobius Microsystems Microsystems Mbius Slide 21 of 21 Questions welcome