LAB #2 Xilinix ISE Foundation Tools Schematic Capture “A Tutorial” ENG2410 Digital Design LAB #2 Xilinix ISE Foundation Tools Schematic Capture “A Tutorial” ENG241/ Lab #2

Lab Objectives Learn the basics of Xilinx ISE tool. Enter your design using Schematic Capture. Implement some simple logic functions on the NEXYS 3 board. Test and Debug your design and verify software simulation and hardware implementation. ENG241/ Lab #2

Xilinx ISE Tool ENG241/ Lab #2

Schematic Capture Sample circuit entered using Schematic Capture. Note that this is not the circuit you will be building ENG241/ Lab #2

Very Important The lab computers employ restore-point software to prevent modification on drive C. This means that if anyone saves their work on Drive “C” IT WILL BE LOST AFTER REBOOTING. The Computers reboot everyday at 4 am automatically. Please save your projects on the “T” Drive and copy it to your “H” drive when you are done working. The “T” drive is common to anyone on that computer, and someone may delete your work accidentally, so always backup your projects on your network “H” drive. Also, to prevent plagiarism of your projects, remove your projects off the “T” drive once they are stored on the network drive. ENG241/ Lab #2

FPGA Power Switch Reset LEDs USB Switches to control input ENG241/ Lab #2

FPGA LUT A B C D Z LUT implementation ENG241/ Lab #2

UCF File It is used to define the Input/Output pin assignment for the FPGA on the NEXYS 3 board. You will use the following assignments in Part 1: NET A LOC = T5; // left most slide switch on NEXYS 3 board NET B LOC = V8 ; // next slide switch on NEXYS 3 board NET C LOC = U8; // third slide switch on NEXYS 3 board NET F LOC = T11; // left most LED on NEXYS 3 board ENG241/ Lab #2

Digilent Adept Tool The Digilent Adept Tool is used to: Test the FPGA board. Program the FPGA board. Check Appendix A in the Tutorial ENG241/ Lab #2

Behavioral Simulation ENG241/ Lab #2

Test Bench BEGIN A_tb <= '0'; -- apply input combination 00 and check outputs B_tb <= '0'; wait for period; assert ((S_tb = '0') and (C_tb = '0')) report "test failed for input combination 00" severity error; ... … A test for you to check your schematic capture with you’re the truth table that you should have. ENG241/ Lab #2

Part 1: Statement Design a 3-input majority circuit that outputs a ‘1’ when the majority of inputs are ‘1’: A B C F 1 …. ENG241/ Lab #2

Part 1: Requirements Complete the truth table. Derive the Boolean function for the Circuit. Draw the circuit diagram (AND, OR, INV) Implement the design using Xilinx ISE Schematic Capture tool Test and Debug your Circuit. Use the UCF file provided to you in the hand-out. ENG241/ Lab #2

Part 2: Statement In this part you will use Xilinx ISE schematic capture tool again to enter your design. The circuit has two inputs (X and Y) and one output (F). The function F is true when X and Y are different, and false when they are the same. ENG241/ Lab #2

Part 2: Requirements Derive the truth table. Derive the Boolean expression for F. Assume X is MSD Draw the circuit diagram. Enter the design using Schematic Capture. Simulate your design. Create the UCF file for this circuit on your own. Verify your Implementation. ENG241/ Lab #2

Academic Misconduct Reports and demos are submitted as a group, but it is a SINGLE group effort You may talk with other groups but sharing codes or reports is NOT ALLOWED Copying reports from previous years is also NOT ALLOWED If we find copying we are REQUIRED to report it